Regulated Cascode Circuit With Feedback for Low-Voltage PSRR
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Solution Overview
Problem
Conventional cascode circuits fail to achieve satisfactorily high output resistance and power supply rejection ratio (PSRR) at low voltages, especially less than 1 V, due to reduced channel length modulation and operational instability.
Innovation Solution
A regulated cascode circuit is designed with P-channel and N-channel metal-oxide semiconductor field-effect transistors (MOSFETs) connected in series, along with a regulation circuit that stabilizes voltages at the drain of PMOS FETs and source of NMOS FETs using control signals, enhancing PSRR and maintaining high output resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional regulated cascode circuit is used to increase output resistance, then output resistance is improved, but power supply rejection ratio (PSRR) is degraded due to noise in power lines
Solution Approach 1:
The patent introduces a regulation circuit as an intermediary between the power supply lines and the cascode circuit. This regulation circuit includes control transistors that actively regulate the gate voltages of the cascode transistors, isolating the high-impedance nodes from power supply noise while maintaining the desired output resistance. The intermediary regulation mechanism filters out harmful power supply fluctuations before they can affect the signal path.
Solution Approach 2:
The patent implements feedback mechanisms where the regulation circuit continuously monitors the gate voltages of the cascode transistors and adjusts them to compensate for power supply noise. By feeding back information about voltage fluctuations and actively correcting them, the system maintains high PSRR while preserving the high output resistance characteristic of regulated cascode circuits.
2Stability of the object's composition
If the third NMOS FET operates in weak inversion region to minimize output voltage swing loss, then output voltage swing is improved, but operational stability is degraded
Solution Approach 1:
The patent dynamically changes the operating parameters of the regulation transistors based on circuit conditions. By adjusting gate voltages and current levels through the regulation circuit, the system can maintain transistors in optimal inversion regions that balance voltage swing performance with operational stability, avoiding the pitfalls of fixed weak inversion operation.
Solution Approach 2:
The patent introduces dynamic control mechanisms where the regulation circuit actively adjusts transistor operating points in real-time based on signal conditions and power supply variations. This dynamic adaptation allows the circuit to maintain stability margins while optimizing voltage swing performance, rather than operating in a fixed weak inversion state.
3Strength
If conventional cascode circuit is used to achieve high output impedance, then output impedance is improved, but channel length modulation effect is reduced due to scale-down
Solution Approach 1:
The regulation circuit acts as an intermediary that compensates for reduced channel length modulation effects in scaled-down technologies. By introducing active voltage control at the gate nodes, the system effectively extends the influence of the cascode structure's output impedance without relying solely on the physical channel length modulation that diminishes in scaled processes.
Solution Approach 2:
The patent changes the control parameters from passive reliance on channel length modulation to active voltage control through the regulation circuit. By adjusting gate voltages dynamically, the system maintains high output impedance characteristics even when physical channel length effects are reduced due to technology scaling.
Data Source
AI summary
A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.