Regulated Cascode CMOS Circuit for Sub-1V Gain and Swing
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Solution Overview
Problem
Analog circuits face challenges in achieving stable operation and sufficient voltage gain at low operating voltages due to increased leakage current and channel length variation, making it difficult to secure large output impedance and swing range, especially in miniaturized systems.
Innovation Solution
A regulated cascode circuit configuration using PMOS transistors with higher threshold voltages than NMOS transistors, coupled with current sources and specific power supply voltage arrangements, allows for stable operation in the strong inversion region, maintaining output impedance and swing range without increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a regulated cascode circuit is designed to operate in weak inversion region to reduce swing range loss, then swing range is improved, but temperature stability deteriorates
Solution Approach 1:
The patent changes the operating parameter of the transistor from weak inversion to strong inversion region operation. This parameter change allows the circuit to achieve both adequate swing range and temperature stability, as strong inversion provides better temperature characteristics while the regulated cascode structure maintains acceptable voltage headroom
Solution Approach 2:
The patent introduces an intermediary transistor (third transistor of opposite conductive type) that acts as a mediator to provide the necessary gate voltage to the cascode transistor. This intermediary element enables the main transistor to operate in strong inversion region while maintaining the regulated cascode functionality, thus achieving both swing range and temperature stability
2Ease of operation
If conventional cascode configuration is used to increase output impedance, then output impedance is improved, but voltage gain deteriorates at low operating voltages
Solution Approach 1:
The patent introduces a third transistor as an intermediary element that actively regulates the gate voltage of the cascode transistor. This intermediary structure provides voltage gain boosting while maintaining high output impedance, overcoming the limitations of conventional cascode at low operating voltages
Solution Approach 2:
The patent changes the operating mode by using a regulated cascode structure where the gate voltage of the cascode transistor is actively controlled rather than fixed. This parameter change enables the circuit to achieve both high output impedance and sufficient voltage gain at low operating voltages below 1V
3Area of moving object
If transistor scale down is performed to reduce device size, then device area is improved, but leakage current increases
Solution Approach 1:
The patent changes the threshold voltage parameter by using a transistor with higher threshold voltage (such as PMOS with higher |Vth| compared to NMOS). This parameter change reduces leakage current in scaled-down devices while maintaining acceptable device area, as higher threshold voltage transistors exhibit lower off-state current
Data Source
AI summary
A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.