Regulator Circuit Rapid Voltage Stabilization via Current Mirror
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Solution Overview
Problem
Semiconductor memory devices face challenges in rapidly stabilizing internal power supply voltages due to large-sized power transistors with high capacitance, leading to prolonged stabilization times and inefficiencies in responding to changes in load current.
Innovation Solution
A regulator circuit incorporating a power transistor, current mirror, and current source configuration that adjusts the gate voltage of the power transistor to rapidly compensate for changes in internal power supply voltage by generating mirrored currents based on reference currents, thereby reducing stabilization times and improving power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a large-sized power transistor is used to supply power to semiconductor memory devices, then the power supply capability is improved, but the stabilization time of internal power supply voltage increases due to large capacitance
Solution Approach 1:
The patent divides the single large power transistor into multiple parallel power transistors (first power transistor and second power transistor). This segmentation reduces the effective capacitance that needs to be charged/discharged individually, allowing faster voltage stabilization while maintaining the same total power supply capability through parallel operation.
Solution Approach 2:
The patent implements dynamic control of power transistor gates through separate control circuits that can independently adjust the switching timing and duration of each power transistor. This dynamic control allows the system to optimize the power supply response characteristics, achieving faster stabilization by controlling the discharge/charge process of gate capacitances in a time-dependent manner.
2Reliability
If the internal power supply voltage is stabilized during a predetermined interval, then the operation credibility of semiconductor memory devices is improved, but the response time to load current changes increases
Solution Approach 1:
The control circuits dynamically adjust the operating state of power transistors based on real-time detection of internal power supply voltage and load current conditions. When load changes are detected, the control circuits can quickly modify gate voltages to accelerate the response, while maintaining stable operation during normal conditions through predetermined interval stabilization.
Solution Approach 2:
The patent incorporates feedback mechanisms where the control circuits continuously monitor the internal power supply voltage and load current, then adjust the power transistor operation accordingly. This feedback loop enables the system to maintain reliability through stable operation while rapidly responding to load changes by detecting voltage deviations and correcting them through adjusted power transistor control.
3Speed
If a current mirror configuration is added to provide mirrored currents, then the compensation speed for voltage changes is improved, but the device complexity increases
Solution Approach 1:
The patent uses current mirror circuits to create copies of reference currents and apply them to the gates of power transistors. The current mirror configuration replicates the reference current waveform and timing characteristics, enabling fast compensation of voltage changes by providing precisely timed current pulses that mirror the desired power supply adjustment profile without requiring complex control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables rapid compensation for changes in internal power supply voltage, reducing stabilization times and improving the efficiency of power management in semiconductor memory devices by dynamically adjusting current magnitudes based on load current changes.
Implementation Method 1
a current mirror configured to provide a first current to a third node, and the current mirror further configured to provide the first node with a second current, the second current having a same magnitude as the first current
Implementation Method 2
a power transistor, a source of the power transistor configured to receive an external power supply voltage, a gate of the power transistor connected to a first node and a drain of the power transistor connected to a second node, the power supply voltage configured to generate an internal power supply voltage
Data Source
AI summary
A regulator circuit includes a power transistor, a current mirror, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to an external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current mirror provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.