Regulator Circuit for Semiconductor Memory Pass Voltage Stabilization
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Solution Overview
Problem
Conventional regulator circuits in semiconductor memory devices experience unstable pass voltage levels during transitions from program to verification operations, leading to increased current consumption and time for stabilization due to varying discharge currents and temperature characteristics.
Innovation Solution
A regulator circuit that includes a discharge circuit and control circuit to automatically control the discharge period of the pass voltage, ensuring it reaches the target level quickly and stabilizes it by comparing bandgap and feedback voltages, and generating control signals to activate the discharge circuit for a predetermined time during operation transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the pass voltage VPASS is discharged through a high resistance value resistor in the regulator to reduce pump current consumption, then current consumption is reduced, but the discharge current becomes unstable and varies with temperature characteristics
Solution Approach 1:
The patent changes the resistance value dynamically by switching between two resistors (first resistor with higher resistance and second resistor with lower resistance) based on operating conditions. This allows the system to optimize between current consumption and discharge current stability by selecting appropriate resistance values for different temperature or operational states.
Solution Approach 2:
The patent introduces dynamic control of the discharge path by using a control circuit that switches between different resistor configurations based on temperature characteristics or operational requirements. This transforms a static high-resistance discharge path into a dynamic system that can adapt to changing conditions, ensuring stable discharge current while maintaining low current consumption.
2Loss of time
If the pass voltage VPASS is discharged quickly to stabilize voltage level during operation transition, then stabilization time is reduced, but current consumption increases due to larger discharge current
Solution Approach 1:
The patent employs periodic or staged discharge action by controlling the switch between different resistor configurations. Instead of a single large discharge current, the system uses controlled discharge phases that balance speed and energy consumption, activating stronger discharge paths only when necessary for rapid stabilization.
Solution Approach 2:
The patent changes resistance parameters dynamically during the discharge process. By switching between high and low resistance values based on real-time voltage level monitoring, the system achieves rapid initial stabilization followed by fine-tuned voltage maintenance, optimizing both stabilization time and current consumption.
3Reliability
If the pass voltage VPASS level is abnormal during program to verification operation switch, then the discharge time becomes long, but the switch may be activated prematurely causing unstable voltage level
Solution Approach 1:
The patent implements feedback control by monitoring the pass voltage VPASS level and using this information to control the discharge circuit activation. The control circuit continuously compares the actual voltage level with the target level and adjusts the discharge operation accordingly, preventing premature switch activation and ensuring stable voltage transition.
Solution Approach 2:
The patent prepares the discharge circuit in advance by pre-configuring the control logic to monitor voltage levels before switching operations. This preliminary monitoring ensures that the discharge circuit is activated at the optimal moment, preventing both premature activation and excessively long discharge times.
Data Source
AI summary
A semiconductor memory device includes a charge pump circuit for generating a pass pump voltage in response to a clock signal and a pump enable signal and a regulator circuit for maintaining the pass pump voltage in the same level as a program pass voltage during a program operation and discharging the program pass voltage during a verification operation so that the program pass voltage has the same level as a verification pass voltage.