Regulator Clock Buffer Current Control for Voltage Step-Up
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Solution Overview
Problem
Voltage step up/down circuits consume unnecessary current due to constant current flow from the output buffer after reaching a steady state, which reduces efficiency.
Innovation Solution
A regulator with a feedback circuit and clock generating circuit that adjusts the clock signals based on boost signals, controlling the driving current to the buffer circuits, thereby regulating the output voltage and reducing unnecessary current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the consumption current of the output buffer is increased to enhance voltage step up and down capability, then the voltage step up/down capability is improved, but unnecessary current consumption increases after reaching steady state
Solution Approach 1:
The patent applies dynamics by making the buffer circuit's operating state variable rather than fixed. The buffer circuit dynamically transitions between a high-current state during voltage transition and a low-current state during steady operation. This is achieved through control circuitry that adjusts the buffer's driving capability based on real-time voltage feedback, allowing the system to optimize current consumption at different operational phases while maintaining voltage step up/down capability when needed.
2Reliability
If constant current flows through the output buffer after steady state is reached, then the voltage regulation is maintained, but unnecessary current is consumed continuously
Solution Approach 1:
The patent implements periodic action through pulse-width modulation (PWM) control of the buffer circuit. Instead of maintaining constant current flow, the buffer operates in periodic pulses during steady state. The control circuitry generates PWM signals that periodically activate the buffer circuit based on voltage feedback, providing just enough current to maintain voltage regulation while allowing the buffer to remain inactive during intervals, thereby eliminating continuous unnecessary current consumption.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the buffer circuit's operating parameters (current level, switching frequency) based on the operational phase. During voltage transitions, the buffer operates at high current with high switching frequency. Once steady state is reached, the control circuitry changes the parameters to low current and reduced switching frequency, maintaining voltage regulation capability while minimizing energy loss through parameter optimization.
Data Source
AI summary
A regulator includes a capacitor connected between a ground terminal and an output terminal at which a first voltage is supplied. The first voltage is higher than a power source voltage supplied to the regulator. A feedback circuit in the regulator is configured to output a boost signal corresponding to a comparison between the first voltage and a threshold voltage value. A clock generating circuit includes an oscillator circuit that outputs an oscillation signal and a buffer circuit that outputs a clock signal according to the oscillation signal. The clock signal has an electric current level that is controlled in accordance with the boost signal. A charge pump outputs the first voltage in accordance with the clock signal.