On-Chip Regulator Mode Detection Using Node Discharge Sensing
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Solution Overview
Problem
Existing power management systems for RF integrated chips face challenges in automatically detecting and switching between internal and external regulator modes without causing current overhead, race conditions, or reliability issues, particularly during power up and operation.
Innovation Solution
A power management system architecture that includes a comparator and control circuit to detect the regulator configuration mode upon chip wake-up, enabling the internal regulator to be completely switched off and set to high-impedance in external regulator mode, using a timer and discharge mechanism to monitor voltage and determine if a node is driven or floating, thereby avoiding race conditions and enabling flexible power supply selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software is used to indicate external regulator mode, then the system can distinguish between internal and external regulator modes, but the solution requires customer-specific software customization and does not work during chip wake-up
Solution Approach 1:
The detection circuit automatically detects the regulator mode without requiring external software intervention. The circuit self-configures by monitoring the voltage at the regulator output node and automatically determines whether an external regulator is present, eliminating the need for customer-specific software customization.
Solution Approach 2:
The detection circuit operates during the chip wake-up sequence before the main system software is executed. By performing the mode detection preliminarily during power-up, the system establishes the correct regulator configuration before any software needs to be loaded or customized.
2Reliability
If a dedicated IO pin is used to detect regulator mode, then the chip can reliably distinguish between internal and external regulator modes, but the solution consumes additional pins and increases cost for IO-limited chips
Solution Approach 1:
The regulator output node serves multiple functions: it is both the power output node for the internal regulator and the detection point for determining external regulator presence. This multi-functional use of existing circuit nodes eliminates the need for dedicated detection pins while maintaining reliable mode detection.
Solution Approach 2:
The power regulation function and mode detection function are merged into a single circuit arrangement. The same node that carries the regulator output voltage is also used as the detection point, combining two functions into one without requiring additional hardware resources.
3Extent of automation
If an internal comparator is used to detect configuration modes, then the chip can automatically detect internal and external regulator modes, but the solution causes false detection when the regulator output is high-Z during OFF condition
Solution Approach 1:
The detection circuit dynamically adjusts its operation based on the regulator state. During wake-up and power-up sequences, the circuit is activated to perform detection when the regulator output is actively driven. During normal operation with the regulator in high-Z OFF state, the detection circuit remains inactive or is prevented from sampling, avoiding false detection of external regulator presence.
Solution Approach 2:
The control circuit is designed to prevent the comparator from sampling the regulator output voltage during conditions when the output is in high-Z state. By anticipating potential false detection scenarios and preventing them beforehand through control logic, the system avoids erroneous mode detection while maintaining automatic detection capability during valid operating conditions.
4Reliability
If a series switch is placed in the power path to avoid race condition, then the race condition between internal and external regulators is prevented, but the solution compromises voltage regulation due to series switch resistance
Solution Approach 1:
The detection circuit performs mode detection during the wake-up sequence before the internal regulator is enabled. By determining the presence or absence of an external regulator preliminarily, the system can configure the power path appropriately before power consumption becomes significant, avoiding the need for series switches that would continuously degrade voltage regulation.
Solution Approach 2:
The power path configuration is dynamically adjusted based on the detected regulator mode. When an external regulator is detected, the internal regulator is kept disabled and its output is maintained in high-Z state, effectively connecting the load to the external regulator without series resistance. When no external regulator is present, the internal regulator is enabled to provide power directly to the load, maintaining optimal voltage regulation without the need for series switches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables automatic detection of regulator modes without additional pins or signals, preventing current overhead and reliability issues, allowing customers to choose between internal and external regulators without architectural constraints, and using standard host commands.
Implementation Method 1
a comparator acting as a detector and a control circuit in said system architecture for detecting if the chip is in the internal regulator configuration mode or external regulator configuration mode
Implementation Method 2
a timer and discharge mechanism to monitor voltage and determine if a node is driven or floating
Data Source
AI summary
A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.