Regulator Mode-Switching Circuit for Fast LP-to-HP Transitions

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Solution Overview

Problem

Current semiconductor devices and memory systems face challenges in improving processing capacity and power management, particularly in efficiently switching between low power (LP) and high power (HP) operation modes, which affects power consumption and data transfer performance.

Innovation Solution

A semiconductor device with a regulator that includes both LP and HP modes, featuring a mode switching circuit that applies terminal voltage to a capacitor during the LP mode to prevent delay in switching to the HP mode, thereby shortening the stabilization period and improving processing capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the regulator switches from LP mode to HP mode, then processing capacity and data transfer performance are improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The regulator dynamically switches between LP and HP modes based on operational requirements. The mode switching circuit enables the regulator to adapt its operating state, transitioning from low-power mode during idle periods to high-power mode during active data transfer, thereby optimizing the balance between processing capacity and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The regulator changes its operating parameters by switching between different modes. In LP mode, the regulator operates with reduced bias currents and lower power consumption. When switching to HP mode, the regulator increases its operating parameters including bias currents and processing capacity to handle high-speed data transfer requirements.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the regulator switches from LP mode to HP mode, then data transfer performance is improved, but stabilization time increases

Engineering Contradiction:
Improvedata transfer performanceVSAvoidstabilization period
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The capacitor is pre-charged to a specific voltage level during LP mode operation. When switching to HP mode, this pre-charged capacitor provides immediate voltage support, reducing the stabilization period. The preliminary charging action ensures that the regulator can quickly transition to high-power operation without experiencing a prolonged stabilization delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The capacitor acts as an intermediary energy storage element that facilitates smooth transition between modes. It stores energy during LP mode and releases it during HP mode activation, mediating the power delivery to minimize voltage fluctuations and reduce the time required for the regulator to stabilize in the new operating state.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If frequent mode switching occurs, then power management efficiency is improved, but switching delay affects performance

Engineering Contradiction:
Improvepower management efficiencyVSAvoidswitching delay
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The mode switching circuit incorporates feedback mechanisms that monitor system state and determine optimal switching timing. By using feedback signals, the regulator can make informed decisions about when to switch modes, ensuring that switching occurs at appropriate moments when it provides maximum power management benefit while minimizing performance impact from switching delays.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances processing capacity by reducing power consumption, shortening the time to active state, and improving data transfer performance by rapidly switching between operation modes, allowing for frequent transitions between LP and HP modes.

Implementation Method 1

a capacitor including a first electrode connected to the output terminal; and a second circuit connected to a second electrode of the capacitor and configured to: (a) electrically disconnect the first circuit from the first capacitor and apply a second voltage to the first capacitor in the first operation mode

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11302400B2Semiconductor device and memory system
Publication Date: 2022.04.12 KIOXIA CORP
  • US11302400B2 patent drawing
  • US11302400B2 patent drawing
  • US11302400B2 patent drawing

AI summary

A semiconductor device includes a first transistor; a first resistor; a second resistor; a first circuit configured to apply a first voltage to the first transistor. The first voltage is based on a difference between a reference voltage and an output voltage divided by the first and second resistors. A first current through the first circuit in a first mode is less than a second current through the first circuit in a second mode. The semiconductor device includes a capacitor connected to the output terminal; and a second circuit connected to the capacitor that: (a) disconnects the first circuit from the capacitor and apply a second voltage to the capacitor in a first mode, and (b) electrically connects the first circuit to the capacitor in the second mode.