Programmable Regulator Ring Oscillator for Phase Realignment

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Solution Overview

Problem

Ring-type voltage controlled oscillators (RO-VCOs) in phase-locked loops experience performance degradation due to high gains and phase noise, leading to jitter performance issues, which existing realignment techniques struggle to effectively address.

Innovation Solution

A programmable regulator voltage controlled ring oscillator (REG-VCO) is introduced, featuring a resistor bank array, PMOS devices, and a realignment portion that adjusts current and pulse width to realign the phase of the ring oscillator, improving phase noise and jitter performance by using a programmable solution to balance noise and jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing realignment techniques are used to address phase noise and jitter in RO-VCOs, then some improvement in performance is achieved, but the techniques struggle to effectively address the performance degradation caused by high gains and phase noise

Engineering Contradiction:
Improvejitter performanceVSAvoidphase noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements a programmable realignment mechanism where the realignment portion can be dynamically configured through programming to adjust its operation. This allows the system to adaptively compensate for phase noise and jitter under different operating conditions, transforming a static realignment approach into a dynamic one that can effectively address performance degradation across varying scenarios.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the realignment portion through programming, enabling adjustment of realignment strength and characteristics. By modifying parameters such as pulse width, amplitude, or timing of realignment signals, the system can optimize the balance between noise reduction and jitter performance, effectively resolving the contradiction between these two harmful factors.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the realignment portion is made programmable to balance noise and jitter, then effective control of phase noise and jitter is achieved, but device complexity increases

Engineering Contradiction:
Improvephase noise and jitter controlVSAvoidprogrammable regulator structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The programmable realignment portion is designed to perform multiple functions: it can adjust realignment strength, modify pulse characteristics, and adapt to different operating conditions all within a single circuit block. This multi-functionality reduces the need for separate dedicated circuits for each adjustment, thereby limiting the increase in device complexity while achieving effective noise and jitter control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a programmable interface or control mechanism that acts as an intermediary between the digital control logic and the analog realignment circuitry. This intermediary layer enables precise control of the realignment portion through programming without requiring direct complex analog adjustments, thus managing device complexity while maintaining effective noise and jitter control.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11764794B2Programmable regulator voltage controlled ring oscillator
Publication Date: 2023.09.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11764794B2 patent drawing
  • US11764794B2 patent drawing
  • US11764794B2 patent drawing

AI summary

Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.