Semiconductor Regulator Circuit Startup Rush Current Suppression
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Solution Overview
Problem
In semiconductor integrated circuits, the steep rise gradient of output voltage during startup can trigger the ESD protection circuit, leading to increased rush current, which hampers the voltage rise to target levels within the required time and prolongs startup time due to shunting of current through the ESD protection circuit.
Innovation Solution
A control circuit is implemented to make the responsiveness of the error amplifier slower at startup than at steady operation by reducing the bias current supplied to the error amplifier, thereby controlling the output transistor's turn-on speed and reducing the rise gradient of the output voltage, preventing the ESD protection circuit from activating prematurely.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the output transistor is turned on quickly at startup to establish conduction path, then the voltage rise speed is improved, but rush current increases and ESD protection circuit activates prematurely
Solution Approach 1:
The error amplifier's responsiveness is dynamically adjusted based on operating conditions. At startup, the error amplifier operates with reduced responsiveness to prevent excessive rush current, while during steady operation, it operates with full responsiveness to maintain fast voltage regulation. This dynamic adjustment resolves the contradiction between fast voltage rise and rush current suppression.
Solution Approach 2:
The bias current supplied to the error amplifier is changed as a control parameter. By reducing the bias current at startup, the error amplifier's responsiveness is slowed down, which in turn slows the turn-on speed of the output transistor and suppresses rush current. During steady operation, the bias current is increased to restore fast responsiveness. This parameter change directly addresses the contradiction.
2Loss of time
If the error amplifier responsiveness is increased to improve voltage regulation speed, then the startup time is reduced, but rush current increases and activates ESD protection circuit
Solution Approach 1:
The error amplifier's responsiveness is made dynamic rather than static. During startup, it operates with slower responsiveness to suppress rush current and prevent ESD activation. Once the system enters steady operation, the responsiveness is increased to reduce startup time for subsequent voltage adjustments. This dynamic behavior resolves the time-loss contradiction.
Solution Approach 2:
The error amplifier operates in different modes during different periods of system operation. During the startup period, it uses a slower response mode. During steady operation periods, it switches to a faster response mode. This periodic switching between operational modes allows the system to optimize performance for each operational phase without suffering from the contradictions present in a single fixed-mode design.
3Object-generated harmful factors
If the bias current to error amplifier is reduced to suppress rush current, then the ESD protection circuit activation is prevented, but the voltage regulation responsiveness deteriorates
Solution Approach 1:
The error amplifier's bias current is dynamically adjusted based on the operational state. During startup when rush current suppression is critical, the bias current is reduced to prevent ESD activation. During steady operation when voltage regulation speed is more important, the bias current is increased to improve responsiveness. This dynamic adjustment resolves the contradiction between preventing ESD activation and maintaining fast voltage regulation.
Solution Approach 2:
The system preliminarily reduces the bias current during the startup phase before the ESD protection circuit can be activated by rush current. This preliminary action of reducing bias current prevents the harmful effect of ESD activation. After the startup phase is complete and the system enters steady operation, the bias current is increased to improve voltage regulation responsiveness, thus resolving the contradiction through time-based preliminary action.
Data Source
AI summary
According to one embodiment, there is provided a semiconductor integrated circuit including an output transistor, an error amplifier, and a control circuit. The output transistor is connected between a first node on an input terminal side and a second node on an output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a third node between the second node and a standard potential. The inverting input terminal is connected to a reference voltage. The output terminal is connected to the gate of the output transistor. The control circuit makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.