Reinforced Semiconductor Layer Stack with Segmented UBM
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Solution Overview
Problem
Semiconductor components, particularly chip scale packages (CSPs), face reliability issues due to stress buffering failures during thermal cycling and drop tests, especially with advanced technology stacks featuring multiple interconnect and dielectric layers of low-K materials, which lead to cracking and delamination.
Innovation Solution
The introduction of reinforcing elements, such as plugs or vias, within the metal and dielectric layers to anchor the stack and distribute stress, combined with a stress buffering system that decouples UBM layers and uses independent, thermomechanically separate stress buffering elements to absorb thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stress buffering layer is provided between the I/O pads and solder balls, then stress absorption during thermal cycling is improved, but the hard UBM layer transmits stresses to adjacent structures causing reliability degradation
Solution Approach 1:
The UBM layer is divided into multiple separate UBM structures, each associated with individual solder balls, rather than a continuous layer. This segmentation prevents stress from one location from transmitting to adjacent structures through the UBM layer, while the stress buffering layer continues to absorb thermal cycling stresses effectively.
Solution Approach 2:
The stress buffering layer acts as an intermediary between the I/O pads and the segmented UBM structures. It absorbs and dissipates thermal expansion stresses before they reach the UBM, preventing the UBM from transmitting these stresses to adjacent structures while maintaining reliable electrical connections.
2Adaptability or versatility
If multiple interconnect and dielectric layers of low-K materials are used in advanced technology stacks, then device functionality is improved, but mechanical strength decreases leading to cracking and delamination
Solution Approach 1:
Reinforcing elements are strategically placed at specific locations within the layer stack, particularly at interfaces between dielectric layers and around high-stress areas. This localized reinforcement strengthens vulnerable regions without affecting the overall low-K material properties and device functionality of the multiple interconnect layers.
Solution Approach 2:
The patent combines low-K dielectric materials with reinforcing elements to create a composite structure. The low-K materials maintain their electrical properties and device functionality, while the reinforcing elements provide the necessary mechanical strength to prevent cracking and delamination in the multi-layer stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mechanical strength and reliability of semiconductor components by reducing deformation and crack formation, allowing for larger wafer-level packaging arrays and improved performance in thermal cycling and drop tests.
Implementation Method 1
stresses will occur as a result of the differences in thermal expansion between the material of the board and, for example, the silicon of a semiconductor
Data Source
AI summary
The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing element having at least one integrated anchor-like part, is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.