Semiconductor Re-interconnection Layer Electrode Positioning
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices with a re-interconnection layer is the occurrence of warpage and difficulty in forming an electrode layer accurately after removing the support substrate, which affects the positioning and alignment of vias and electrode layers, leading to potential short circuits and hindering device downsizing.
Innovation Solution
A semiconductor device is manufactured with a re-interconnection layer that includes an insulating layer, interconnections, first vias, and second vias, where the electrode layer is formed in a recess created by etching the exposed surfaces of the first vias, using electroless plating to ensure high position accuracy and prevent short circuits, and bumps are bonded to the electrode layer made of a different metal material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a re-interconnection layer is used instead of a print board to achieve low profile, then the device height is reduced, but warpage occurs after support substrate removal making electrode layer formation difficult
Solution Approach 1:
The patent performs preliminary actions by forming the electrode layer on the support substrate before removal, and creating recesses in the re-interconnection layer before bump bonding. This ensures that critical alignment operations are completed when the support substrate is still present to provide mechanical stability, eliminating warpage-related positioning errors.
Solution Approach 2:
The patent replaces mechanical alignment methods with etching-based recess formation. Instead of relying on mechanical positioning of electrode layers on a warprone re-interconnection layer, the invention uses chemical etching to create precise recesses that guide electrode layer placement, ensuring accurate positioning independent of substrate warpage.
2Adaptability or versatility
If the support substrate is removed to enable bump bonding, then device integration is improved, but warpage occurs causing misalignment of vias and electrode layers
Solution Approach 1:
The patent performs preliminary via formation and electrode layer patterning while the support substrate is still present, ensuring precise alignment before the substrate provides structural support. This sequence prevents misalignment that would occur if these operations were attempted after support removal and warpage development.
Solution Approach 2:
The support substrate acts as an intermediary during critical manufacturing steps, providing a stable platform for precise via and electrode layer formation. The substrate is removed only after its mediating function has enabled accurate alignment, at which point the already-formed structures are immune to warpage effects.
3Manufacturing precision
If electroless plating is used to form the electrode layer, then position accuracy is improved and short circuits are prevented, but additional manufacturing steps are required
Solution Approach 1:
The electroless plating process is self-aligning, automatically depositing metal only in recessed areas where the electrode layer is needed. This self-service mechanism eliminates the need for complex alignment systems and additional positioning steps, as the chemistry itself ensures precise electrode layer placement and prevents short circuits between adjacent electrodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves high position accuracy of the electrode layers and prevents short circuits, enabling a low-profile semiconductor device with improved manufacturing efficiency and reduced warpage issues.
Implementation Method 1
forming an electrode layer in the recess by electroless plating
Implementation Method 2
forming a recess in a lower surface of the insulating layer by etching exposed surfaces of the first vias
Data Source
AI summary
According to one embodiment, a semiconductor device includes a re-interconnection layer, bumps, chips, and a resin member. The bumps are provided on a first surface of the re-interconnection layer. The chips are stacked on a second surface of the re-interconnection layer. The resin member is provided on the second surface, and covers the chips. The re-interconnection layer includes an insulating layer, an interconnection, a first via, an electrode layer, and a second via. The interconnection is provided in the insulating layer. The first via is provided in the insulating layer and connected to the interconnection. The electrode layer is provided in the insulating layer, formed of a metal material different from a material of the first via, exposed on the first surface, and connected to the first via and the bumps. The second via is provided in the insulating layer, and connected to the interconnection and the chips.