RELACS Spacer Patterning for Sub-40nm Semiconductor Devices
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming ultra-fine patterns due to resolution limits of photolithography tools, leading to complex processes, high costs, and misalignment issues in double exposure and double patterning technologies, particularly when trying to create patterns smaller than 40 nm.
Innovation Solution
A method using a Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) layer formed by spin-on-coating, with an over-coating film to inhibit acid generation and induce cross-linking reactions, allowing for the formation of spacers as masks without an etch-back process, simplifying the spacer patterning technology (SPT) and reducing manufacturing costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double exposure technology is used to improve resolution and extend process margin, then pattern resolution is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the etch-back process from the conventional SPT flow, keeping only the essential spacer formation steps. This reduces process complexity while maintaining the ability to form fine patterns, thereby resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The patent modifies the chemical composition and curing characteristics of the RELACS layer to enable spacer formation without etch-back. By changing the material parameters (chemistry and curing behavior), the process achieves fine pattern formation with reduced complexity
2Manufacturing precision
If double patterning technology is used to form smaller pitch patterns, then manufacturing precision is improved, but turn-around-time and productivity decrease
Solution Approach 1:
The patent performs preliminary curing of the RELACS layer to form spacers before the etch-back step, allowing spacer widths to be defined early in the process. This preliminary action enables fine pitch patterns to be formed without extending the overall turn-around-time, resolving the contradiction between manufacturing precision and productivity
3Manufacturing precision
If conventional SPT with etch-back process is used to form spacers, then spacer patterning precision is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the etch-back process step from the conventional SPT sequence while maintaining spacer patterning precision through controlled curing of the RELACS layer. This extraction of unnecessary steps reduces process complexity and manufacturing cost without sacrificing precision
4Device complexity
If ArF exposer with numerical aperture less than 1.2 is used for single exposure, then device complexity is reduced, but manufacturing precision deteriorates for patterns less than 40 nm
Solution Approach 1:
The patent introduces the RELACS layer as an intermediary material that enables fine pattern formation through chemical shrinkage and spacer formation, allowing the use of simpler ArF exposers with lower numerical apertures while achieving high manufacturing precision for sub-40 nm patterns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of fine semiconductor patterns with improved precision and reduced complexity, eliminating the need for multiple exposure processes and minimizing misalignment, while allowing for easier adjustment of spacer widths, thus enhancing the efficiency and cost-effectiveness of the semiconductor manufacturing process.
Implementation Method 1
induce a cross-linking reaction between the RELACS layer and sidewalls of the photoresist pattern
Implementation Method 2
forming a Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) layer by a spin-on-coating method
Data Source
AI summary
A method for forming a pattern of a semiconductor device comprises: forming a stacked film including an underlying layer, an antireflection film and a photoresist film over a semiconductor substrate; coating an over-coating composition over the photoresist film to form an over-coating film; performing an exposing and developing process with a cell mask on the photoresist film where the over-coating film is formed to form a photoresist pattern; forming a silicon-containing-RELACS layer over the antireflection film including the photoresist pattern where the over-coating film is formed; removing the over-coating film and the silicon containing RELACS layer on the photoresist pattern to form a spacer of the silicon containing RELACS layer at sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the antireflection film and the underlying layer with the spacer of the silicon containing RELACS layer as a mask to form an antireflection pattern and an underlying pattern.