Relative Address Generation in Processor Design
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Solution Overview
Problem
Converting a single instruction with relative addressing to two instructions consumes ALU resources and introduces a delay penalty, especially in processors with multiple ALU stages, impacting performance.
Innovation Solution
A processor design that includes an address generator to derive an absolute address from a relative address in one clock cycle, allowing concurrent address generation and data retrieval, and utilizing multiple address generators and register banks to support simultaneous operations across multiple ALUs and data crossbars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If relative addressing is converted to two instructions (one to compute absolute address, one to execute operation), then the addressing mode is compatible with existing ALU operations, but ALU resources are consumed and instruction execution time increases
Solution Approach 1:
The processor is divided into separate functional units: an address generator unit that computes absolute addresses from relative addresses, and execution units (ALUs) that perform operations. This segmentation allows address computation to occur in parallel with data retrieval, eliminating the sequential dependency that reduced throughput.
Solution Approach 2:
An address generator unit acts as an intermediary between the instruction stream and the execution units. This dedicated component handles address computation separately from the ALU, preventing ALU resource consumption and allowing simultaneous address generation and data retrieval through multiple read ports.
2Reliability
If relative addressing conversion is performed sequentially, then instruction dependency is maintained, but delay penalty increases especially in multi-stage ALUs
Solution Approach 1:
The address generator computes the absolute address in advance, before the execution unit needs it. This preliminary action allows the data retrieval to proceed in parallel, reducing the overall execution delay while maintaining proper instruction dependency through the architectural interface.
Solution Approach 2:
The processor maintains continuous operation by allowing address generation and data retrieval to occur simultaneously through different functional units. Multiple read ports enable continuous data flow to execution units without waiting for sequential address computation, eliminating idle cycles.
3Measurement precision
If multiple instructions are used to handle relative addressing, then addressing accuracy is maintained, but ALU resource consumption increases
Solution Approach 1:
The address computation function is extracted from the ALU and placed in a dedicated address generator unit. This extraction allows the ALU to focus solely on execution operations while the address generator handles address computation, reducing ALU resource consumption without compromising addressing accuracy.
Solution Approach 2:
The address generator unit serves multiple purposes: it computes absolute addresses from relative addresses, provides addresses to multiple execution units simultaneously, and interfaces with the instruction stream. This multi-functionality allows accurate address computation without requiring dedicated ALU resources for each operation.
Data Source
AI summary
Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address comprised of a base address and an offset, obtains a base value for the base address, sums the base value with the offset, and provides an absolute address corresponding to the relative address. The storage unit receives the base address and provides the base value to the address generator. The storage unit also receives the absolute address and provides data at this address. The address generator may derive the absolute address in a first clock cycle of a memory access. The storage unit may provide the data in a second clock cycle of the memory access. The storage unit may have multiple (e.g., two) read ports to support concurrent address generation and data retrieval.