Relative Hardware Clocking in High-Level Programming
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Solution Overview
Problem
Existing programming tools lack convenient and flexible means for specifying and implementing relative hardware clocking in programs deployed to programmable hardware, particularly when different execution clock rates are unspecified.
Innovation Solution
A system and method for specifying and implementing relative hardware clocking in a high-level programming language, where user input defines a rational ratio of execution rates for code portions, and a hardware configuration program is automatically generated to control the execution of these code portions on programmable hardware elements, using tools like LabVIEW to create graphical programs and compile them into hardware configuration programs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If prior art programming tools are used, then programs can be deployed to programmable hardware, but convenient and flexible means for specifying and supporting relatively timed code is not provided
Solution Approach 1:
The patent introduces a compiler as an intermediary tool that automatically generates hardware configuration programs from high-level source code. The compiler includes a clocking analysis module that analyzes the source code to determine relative execution rates of different code portions and automatically generates appropriate clocking configurations, eliminating the need for programmers to manually specify complex hardware clocking parameters.
Solution Approach 2:
The system enables self-service by allowing the compiler to automatically perform clocking analysis and generate hardware configuration programs without requiring manual intervention from the programmer. The clocking analysis module autonomously determines execution rates and generates the necessary clocking infrastructure, making the process convenient and flexible while reducing complexity.
2Manufacturing precision
If manual hardware configuration is used, then precise control over execution rates is possible, but the process becomes complex and less flexible
Solution Approach 1:
The patent replaces manual mechanical configuration processes with an automated software-based compiler system. The clocking analysis module uses algorithmic analysis to determine execution rates and generate hardware configuration programs, substituting the manual mechanical process of configuring hardware clocks with an automated software process that maintains precision while reducing complexity.
Solution Approach 2:
The system automatically determines execution rate parameters through clocking analysis of the source code. The compiler analyzes the program structure and automatically sets the clocking parameters (execution rates for different code portions) based on the specified rational ratios, maintaining manufacturing precision while eliminating the need for manual parameter specification.
3Productivity
If different execution clock rates are specified for code portions, then resource optimization is achieved, but the specification process becomes more difficult
Solution Approach 1:
The compiler acts as an intermediary that automatically translates high-level source code into hardware configuration programs with optimized clocking. The clocking analysis module analyzes the source code to identify code portions that can execute at different rates and automatically generates the appropriate clocking configuration, achieving resource optimization without requiring the programmer to manually specify execution rates.
Solution Approach 2:
The system achieves self-service by enabling the compiler to automatically perform resource optimization through clocking analysis. The clocking analysis module autonomously determines which code portions should execute at different rates and generates the corresponding hardware configuration, making resource optimization easy while maintaining productivity benefits.
Data Source
AI summary
System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion.