Relative Offset Branching in Fixed-Width RISC Architectures
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Solution Overview
Problem
In RISC architectures, the fixed instruction word width limits the address bits available for displacement or absolute address branch instructions, restricting the ability to support long branches within a full address range.
Innovation Solution
Implementing relative offset branching by fetching a branch instruction with a separate relative offset value that is formatted as a multiple of the fixed instruction width, allowing it to be added to the program counter value to form a branch target address, thereby enabling redirection of execution to any address within the supported range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed instruction word width is used in RISC architecture, then instruction simplicity and execution rate are improved, but the address bits available for displacement or absolute address branch instructions are limited, restricting the ability to support long branches
Solution Approach 1:
The invention segments the branch addressing into two parts: a base address from the fixed-width instruction word and an offset from separate memory locations. This allows the instruction word to remain simple and fixed-width while extending the effective address range through the combination of base address and offset, resolving the contradiction between instruction simplicity and address range support.
Solution Approach 2:
The invention introduces an intermediary mechanism where offset values are stored in separate memory locations (offset memory) and fetched as needed. This intermediary storage allows the system to extend addressing capability beyond the fixed instruction word width without changing the instruction format, thereby maintaining high instruction execution rate while supporting long branches.
2Adaptability or versatility
If additional address bits are used outside the instruction word to support long branches, then the addressable range is expanded, but the instruction format becomes more complex
Solution Approach 1:
The invention extracts the offset information from the instruction word and places it in separate memory locations. This extraction allows the instruction word to maintain its simple fixed format while the addressable range is extended through the combination of the base address in the instruction and the offset fetched from memory, thus avoiding instruction format complexity.
Solution Approach 2:
The invention adds a temporal dimension to address storage by fetching offset values from memory at different times rather than including all address bits simultaneously in the instruction word. This dimensional change allows extended addressing capability without increasing instruction width or format complexity.
Data Source
AI summary
Embodiments relate to a method and computer program product for relative offset branching in a reduced instruction set computing (RISC) architecture. One aspect is a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A relative offset value is acquired from the instruction stream. The relative offset value is formatted as an offset relative to a program counter value and sized as a multiple of the fixed instruction width. The relative offset value is added with the program counter value to form a branch target address value. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.