Relative Timing Characterization for Asynchronous Circuit Integration
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Solution Overview
Problem
Clocked design methodologies in electronic design automation (EDA) tools primarily support flip-flops and latches, limiting the integration and optimization of asynchronous circuits due to their reliance on discrete clock cycles, which hinders the application of alternative timing methods.
Innovation Solution
The development of a method to characterize timed circuit modules using relative timing, enabling their integration into clocked-based EDA tools by creating path-based or frequency-based constraints, allowing for accurate timing analysis and optimization within existing design flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clocked design methodologies are used in EDA tools, then discrete clock cycle control is achieved, but integration and optimization of asynchronous circuits are limited
Solution Approach 1:
The patent introduces relative timing constraints as an intermediary mechanism that bridges asynchronous circuit behavior with clocked EDA tool workflows. By defining timing relationships between signal events without requiring global clock synchronization, the system enables asynchronous circuits to be analyzed and optimized within traditional clocked design environments, thus resolving the contradiction between adaptability and complexity
2Adaptability or versatility
If relative timing constraints are implemented, then asynchronous circuits can be integrated into clocked EDA tools, but additional timing characterization is required
Solution Approach 1:
The patent performs preliminary timing characterization by automatically generating relative timing constraints from circuit netlists during the design phase. The system identifies all relevant signal paths and pre-computes timing relationships between events, storing them in a format compatible with EDA tools. This preliminary action eliminates the need for manual timing analysis later, reducing the perceived complexity while enabling broad compatibility
3Adaptability or versatility
If traditional clocked design methods are used, then discrete timing control is achieved, but alternative timing methods cannot be fully utilized
Solution Approach 1:
The patent implements dynamic timing analysis by allowing timing constraints to be defined relative to actual signal event occurrences rather than fixed clock cycles. The system adapts timing measurements to the specific behavior of each circuit path, capturing variations in propagation delays and event timing that static clocked models cannot represent. This dynamic approach maintains measurement precision while enabling support for asynchronous and other alternative timing methods
Data Source
AI summary
Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point of convergence (poc) events, wherein the two poc events include a first poc event (poc0) and a second poc event (poc1). The EDA tool can generate a maximum target delay for a first poc event path between the pod event and the first poc event. The EDA tool can generate a minimum target delay for a second poc event path between the pod event and the second poc event. The EDA tool can then optimize the circuit model using the maximum target delay and the minimum target delay.