Relaxation Reduction Liner for Semiconductor STI

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Solution Overview

Problem

Mechanical relaxation of stressed semiconductor layers during shallow trench isolation (STI) formation leads to reduced carrier mobility and increased transistor threshold voltage variability in semiconductor devices.

Innovation Solution

A relaxation reduction liner with high Young's modulus materials like aluminum oxide or hafnium oxide is applied on the dielectric body and adjacent sidewall of the stressed semiconductor layer to maintain mechanical continuity and reduce relaxation, thereby enhancing the stability of the stressed semiconductor layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a mask layer is removed after STI formation, then the isolation trench is completed, but mechanical relaxation occurs at the edge of the stressed semiconductor layer contacting the dielectric body

Engineering Contradiction:
ImproveSTI formation processVSAvoidmechanical continuity of stressed semiconductor layer
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

A relaxation reduction liner is formed on the dielectric body before the mask layer is removed. This preliminary action prevents mechanical relaxation from occurring when the mask layer is subsequently removed, thereby maintaining the mechanical continuity of the stressed semiconductor layer while still completing the STI formation process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The relaxation reduction liner acts as an intermediary between the dielectric body and the stressed semiconductor layer. It transfers and distributes the mechanical stress, preventing the concentration of stress at the edge that would otherwise cause mechanical relaxation and divot formation when the mask layer is removed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the mask layer is removed after STI formation, then the isolation structure is finalized, but carrier mobility is reduced due to mechanical relaxation

Engineering Contradiction:
Improveisolation structure completionVSAvoidcarrier mobility
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The relaxation reduction liner is formed in advance on the dielectric body before mask layer removal. This preliminary protective measure ensures that when the mask layer is removed to complete the isolation structure, the stressed semiconductor layer maintains its mechanical integrity and carrier mobility is preserved.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If the mask layer is removed after STI formation, then the trench is fully exposed, but transistor threshold voltage variability increases due to mechanical relaxation

Engineering Contradiction:
Improvetrench exposureVSAvoidtransistor threshold voltage variability
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The relaxation reduction liner is deposited on the dielectric body before mask removal. This preliminary action prevents the mechanical relaxation that would otherwise occur upon mask removal, thereby maintaining consistent transistor threshold voltage and reducing variability while still achieving full trench exposure.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces mechanical relaxation, maintaining carrier mobility and reducing transistor threshold voltage variability, thus improving the performance and reliability of semiconductor devices.

Implementation Method 1

the mechanical relaxation is elastic and may result in a divot or gap being formed between a sidewall of the stressed semiconductor layer and an adjacent sidewall of the STI

Methodology Applied
Scientific EffectElasticity: Elasticity

Implementation Method 2

As the hard mask is removed, a mechanical relaxation of the stressed semiconductor layer occurs at an edge thereof that contacts the dielectric body

Methodology Applied
Scientific EffectStress Relaxation: Stress Relaxation

Data Source

PatentUS10204982B2Semiconductor device with relaxation reduction liner and associated methods
Publication Date: 2019.02.12 STMICROELECTRONICS INT NV
  • US10204982B2 patent drawing
  • US10204982B2 patent drawing
  • US10204982B2 patent drawing

AI summary

A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.