Relaxed Cache Coherence via Invalidate Commands
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Solution Overview
Problem
Conventional parallel processing architectures face challenges in maintaining coherence between multiple caches accessed by different threads, leading to increased bandwidth consumption and latency due to the need to broadcast write operations across all caches.
Innovation Solution
A system and method that employs a memory barrier instruction to ensure coherence between caches by transmitting an invalidate command to sibling caches, allowing them to process pending invalidate commands before accepting new read or write requests, thereby maintaining relaxed coherency and reducing unnecessary bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write operations are broadcast to all caches to maintain coherence, then cache coherence is improved, but bandwidth consumption increases
Solution Approach 1:
The patent segments the cache coherence maintenance mechanism by introducing separate invalidate commands targeted at specific sibling caches rather than broadcasting to all caches. This allows selective invalidation only where needed, reducing unnecessary bandwidth consumption while maintaining coherence where required.
Solution Approach 2:
The patent uses invalidate commands as intermediaries to maintain coherence. Instead of directly broadcasting write operations to all caches, the system sends invalidate commands through the interconnect to sibling caches, which then update their own cache lines. This intermediary mechanism reduces bandwidth while ensuring coherence.
2Reliability
If write operations are broadcast to all caches to maintain coherence, then cache coherence is improved, but latency increases
Solution Approach 1:
By segmenting the coherence maintenance process into targeted invalidation commands rather than broadcast operations, the system reduces the time required to propagate changes. Only sibling caches receive invalidation commands, eliminating unnecessary propagation delays to unrelated caches.
Solution Approach 2:
The system performs preliminary invalidation actions by sending invalidate commands to sibling caches before the writing cache actually completes its write operation. This allows sibling caches to prepare for potential reads without waiting for the complete write cycle, reducing latency.
3Productivity
If multiple caches are used by different threads to improve parallelism, then processing throughput is improved, but coherence maintenance complexity increases
Solution Approach 1:
The patent segments the coherence maintenance responsibility by assigning specific invalidation tasks to sibling caches. Each cache only needs to manage invalidation for its own sibling caches, dividing the overall complexity into smaller, independent management units that can operate in parallel.
Solution Approach 2:
Sibling caches perform self-service by automatically receiving and executing invalidation commands without requiring intervention from the writing cache or external control mechanisms. This self-service approach simplifies the overall coherence maintenance architecture by eliminating the need for complex coordination protocols.
Data Source
AI summary
One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.