Relay Apparatus for Semiconductor Test Command Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In test apparatuses for semiconductor devices, the propagation time differences between commands to the test unit and the timer apparatus can cause mismatched execution orders, leading to pointless wait times when read commands are inserted to synchronize processes.
Innovation Solution
A relay apparatus is introduced to relay commands between the control apparatus and the test unit, ensuring that the execution order of processes by the test unit and the timer apparatus matches the command issuance order, and allowing the control apparatus to perform subsequent processes without waiting for read responses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read command is inserted before the timer initiation command to synchronize execution order, then the execution order of processes matches the command issuance order, but the control apparatus experiences pointless wait time while waiting for read response
Solution Approach 1:
An interrupt register is introduced as an intermediary mechanism between the timer apparatus and the control apparatus. The timer apparatus writes to the interrupt register when its process completes, and the control apparatus checks this register to determine whether to proceed with subsequent commands. This intermediary allows the control apparatus to continue issuing commands without waiting for timer completion, thereby eliminating pointless wait time while maintaining execution order accuracy.
2Reliability
If the control apparatus waits for read response from test unit before issuing timer initiation command, then execution order is synchronized, but overall processing speed decreases
Solution Approach 1:
The interrupt register serves as a mediator that decouples the timer apparatus and control apparatus communication from the critical command issuance path. The control apparatus can issue commands to the test unit independently, while the timer apparatus autonomously manages its own execution and signals completion through the interrupt register. This architecture maintains process synchronization reliability while significantly improving processing speed by eliminating sequential waiting.
Data Source
AI summary
Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a first communicating section that receives a command from the control apparatus to the relay apparatus and transmits the command to the test unit; a second communicating section that receives a return command that is transmitted back to the relay apparatus by the test unit that received the command; and an executing section that executes a process designated by the return command, in response to the second communicating section receiving the return command.