Relay Cell Backside Signal Routing for IC Congestion Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of transistors in integrated circuits (ICs) leads to design and fabrication issues such as lack of pin access and routing congestion, as existing back side techniques have not fully utilized the back side routing resources.
Innovation Solution
A relay cell structure is introduced in the IC to route signals on the back side using metal layers including backside metal 0 (BM0) lines, backside metal 1 (BM1) lines, and inner metals, with connections between the inner metals and both back side and front side layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are packed more densely in a smaller chip volume, then transistor density is improved, but routing congestion and pin access issues worsen
Solution Approach 1:
The patent introduces back-side routing as a third dimension for signal transmission, moving beyond the traditional two-dimensional front-side routing plane. By utilizing metal layers (BM0, BM1, BM2) on the back side of the chip, the invention creates additional routing space that does not interfere with front-side transistor placement and interconnect, thereby resolving routing congestion while maintaining high transistor density.
2Ease of manufacture
If back side metal layers are used for power supply only, then power distribution is simplified, but routing resource utilization is insufficient
Solution Approach 1:
The patent transforms the back-side metal layers from single-function power distribution structures into multi-functional routing resources. The same metal layers (BM0, BM1, BM2) that provide power supply are also configured to carry data signals between logic cells through relay cells, enabling the back side to serve both power distribution and signal routing functions simultaneously, thereby maximizing resource utilization.
3Adaptability or versatility
If relay cells are introduced for back side signal routing, then routing flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges the relay cell structure with existing logic cell architectures by integrating back-side routing functionality into standard cell designs. The relay cells utilize the same manufacturing processes and material layers as conventional cells, combining signal routing functions with power distribution infrastructure, thereby reducing the incremental complexity introduced by back-side routing.
Data Source
AI summary
Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.