Network Relay Clock Cutoff Circuit for Dynamic Power Reduction
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Solution Overview
Problem
Current network relay apparatuses face challenges in reducing power consumption while maintaining performance, particularly in varying load conditions and preventing packet loss during frequency adjustments.
Innovation Solution
A network relay apparatus with a clock generation circuit, load detector, and clock cutoff circuit that adjusts the frequency of clock signals based on detected load, partially eliminating clock pulses to reduce power consumption without causing packet loss, using multiple clock generation and cutoff circuits for individual partial circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the operating frequency of the processing circuit is reduced to save power, then power consumption decreases, but the processing speed and data transmission capability deteriorate
Solution Approach 1:
The patent applies dynamic frequency adjustment by using a load detector to monitor processing circuit load and a clock cutoff circuit to dynamically adjust the clock signal frequency. When load is high, full frequency is maintained for maximum processing speed; when load is low, frequency is reduced to save power. This dynamic adaptation resolves the contradiction between power consumption and processing speed.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal based on detected load conditions. The clock cutoff circuit selectively removes clock pulses to achieve frequency scaling - reducing frequency when full performance is not needed to lower power consumption, while maintaining high frequency when processing demands require maximum performance.
2Speed
If clock signal frequency is adjusted using oscillator, multiplier or frequency divider, then operating frequency changes, but the adjustment time increases and packet loss may occur
Solution Approach 1:
The patent uses a buffer circuit to preliminarily store data packets before frequency adjustment occurs. When the clock frequency needs to change, the buffer ensures that any packets being processed are completed or stored safely, preventing packet loss. This preliminary buffering action allows rapid frequency switching without compromising data integrity.
Solution Approach 2:
The buffer circuit acts as an intermediary between the processing circuit and the clock frequency adjustment mechanism. It decouples the data flow from the frequency changes, allowing the clock frequency to be adjusted rapidly without directly affecting ongoing data processing, thus preventing packet loss while enabling fast frequency transitions.
3Use of energy by moving object
If the clock signal is completely cut off to maximize power saving, then power consumption decreases significantly, but the processing circuit cannot handle incoming data causing packet loss
Solution Approach 1:
The patent applies partial clock cutoff rather than complete cutoff. The clock cutoff circuit selectively removes a portion of clock pulses based on detected load conditions, achieving partial power saving while maintaining sufficient clocking to handle incoming data. This partial action resolves the contradiction by providing enough clock cycles to prevent packet loss while reducing power consumption compared to full-frequency operation.
Solution Approach 2:
The patent implements a feedback mechanism where the load detector continuously monitors processing circuit load and feeds this information to the clock cutoff circuit. Based on this feedback, the clock cutoff circuit adjusts the degree of clock pulse cancellation dynamically - maintaining full clocking when load is high to prevent packet loss, and increasing cutoff when load is low to maximize power saving.
Data Source
AI summary
A network relay apparatus includes: a clock generation circuit, a processing circuit, a load detector and a clock cutoff circuit. The clock generation circuit is configured to generate a clock signal having periodical clock pulses. The processing circuit is configured to operate in synchronism with the clock pulses, in order to process data that is to be relayed by the network relay apparatus. The load detector is configured to detect a load of processing by the processing circuit. The clock cutoff circuit is configured to cut off supply of the clock pulses from the clock generation circuit to the processing circuit in order to partially eliminate the clock pulses at a rate corresponding to the load detected by the load detector and to provide the clock signal having the partially eliminated clock pulses to the processing circuit.