Relay Device Dynamic Route Selection for Memory Access Load
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Solution Overview
Problem
Conventional semiconductor systems fail to effectively decentralize memory access loads and achieve low latency network transmission, particularly when dealing with varying traffic characteristics and memory access loads that change moment by moment, leading to interference between traffics with different latency requirements.
Innovation Solution
A semiconductor system with a relay device that selects a memory and transmission route based on load values of nodes and routes, using a low latency route selector that considers factors like buffer amount, latency, throughput, and jitter of nodes, and data length, bus width, and bus band, to optimize data transmission and alleviate memory access loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a round robin method is used to determine memory assignment, then the memory access load is distributed, but the memory assignment does not adapt to moment-by-moment load changes and traffic characteristics
Solution Approach 1:
The patent applies dynamics by transitioning from a static round-robin memory assignment method to a dynamic selection mechanism. The relay device continuously monitors traffic characteristics (such as packet size, interval, and buffer status) and dynamically adjusts memory assignment and route selection in real-time. This allows the system to adapt to moment-by-moment load changes and traffic pattern variations, resolving the contradiction between adaptability and productivity.
2Device complexity
If all traffic is transmitted through the same network, then the network structure is simple, but traffic with different latency requirements interferes with each other
Solution Approach 1:
The patent applies segmentation by dividing the network traffic into different categories based on latency requirements. The relay device segments traffic into high-latency-tolerance flows and low-latency-tolerance flows, routing them through different paths or processing priorities. This segmentation allows simple network infrastructure to support differentiated latency performance, resolving the contradiction between network simplicity and latency reliability.
Solution Approach 2:
The patent applies local quality by providing differentiated service characteristics at the relay device level. Instead of treating all traffic uniformly, the system applies local quality differentiation by prioritizing low-latency traffic and applying specific buffering strategies to high-latency traffic. This allows the network to maintain simple overall structure while achieving reliable latency performance for critical traffic types.
3Productivity
If memory access load is decentralized using multiple memories, then the bus crowding is reduced, but the transmission route selection does not consider real-time load conditions
Solution Approach 1:
The patent applies feedback by implementing a monitoring mechanism that collects real-time information about traffic conditions, buffer status, and memory access patterns. The relay device uses this feedback information to dynamically adjust route selection and memory assignment decisions. This feedback loop ensures that the system not only decentralizes memory access load but also adapts route selection to real-time conditions, resolving the contradiction between load distribution and route adaptability.
Data Source
AI summary
Highly efficient and low latency network transmission in consideration of a difference in the traffic characteristic and a memory access load which changes moment by moment is realized. A relay device transmits data on a networked communication bus between a bus master and a memory. The relay device includes a delay time processor for obtaining information on processing delay time in other relay devices located on a plurality of transmission routes on which the data is transmitted; and a low latency route selector for selecting a memory and one of transmission routes to the memory, among the plurality of transmission routes, based on obtained information on the processing delay time regarding the plurality of transmission routes.


