Relay Logic Circuit Verification for Failure Event Safety
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Solution Overview
Problem
Current verification methods for relay logic circuits do not adequately ensure safety when failure events occur, such as unintentional contact or disconnection, as they primarily focus on normal operational performance without addressing safety during failures.
Innovation Solution
A verification-processing device and method that acquires a circuit logic model represented by an evaluation expression, including logical expressions for failure events, to determine the logical state of relay outputs when failures occur, ensuring safety by representing and analyzing potential unsafe states in relay logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification is performed using conventional circuit simulators focusing on normal operation, then basic functional verification is achieved, but safety verification during failure events cannot be performed
Solution Approach 1:
The verification process is segmented into two distinct modes: normal operation verification and failure event verification. The system separates the verification of basic functions from the verification of safety during failures, allowing each to be performed with appropriate methods and assumptions without interfering with the other.
Solution Approach 2:
The system performs preliminary identification of failure events and their associated unsafe states before actual verification. By pre-defining what constitutes a failure event (element failure, connection line disconnection, unintended conduction) and their potential unsafe states, the system prepares the verification framework in advance to systematically check safety conditions.
2Reliability
If comprehensive failure event verification is implemented, then safety during failures is verified, but verification complexity increases
Solution Approach 1:
The system creates a logical model (copy) of the relay logic circuit that mirrors the physical circuit's structure and behavior. This logical model includes representations of relays, elements, connection lines, and their relationships, allowing verification to be performed on the model without physically testing the actual circuit under failure conditions.
Solution Approach 2:
The verification system changes parameters by introducing failure event flags and unsafe state indicators to the logical model. By modifying the model to include these additional parameters that represent failure conditions, the system can systematically evaluate safety without physically altering or damaging the actual circuit.
3Measurement precision
If logical expressions for failure events are added to the circuit logic model, then failure state determination is enabled, but model complexity increases
Solution Approach 1:
The logical expressions are segmented into distinct components: normal operation expressions, failure event expressions, and unsafe state determination expressions. Each segment handles a specific aspect of verification, making the overall model more manageable despite the increased comprehensiveness.
Solution Approach 2:
The logical model is designed to be universal by incorporating expressions that can handle both normal operation and failure events within a single unified framework. The same logical model structure serves multiple purposes: verifying normal functionality, identifying failure events, and determining unsafe states, rather than requiring separate models for each function.
Data Source
AI summary
The verification-processing device includes an acquisition unit that is configured to acquire a circuit logic model represented by an evaluation expression represented by a logical expression taking as variables, a relay, an element, and a connection line that form a relay logic circuit to be verified, the evaluation expression including at least a logical expression for a case where a failure event occurs in the relay logic circuit; and a determination unit that is configured to determine the logical state of an output of the relay when a failure event occurs in the element or the connection line, based on the circuit logic model.