Relay Processor Proxy for Inaccessible I/O Communication

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Solution Overview

Problem

Computing devices in industrial process control and automation systems often cannot communicate with inaccessible input/output (I/O) devices due to electrical or logical incompatibilities, hindering interaction with sensors and actuators.

Innovation Solution

A relay processor is introduced to facilitate communication between a primary processor and an inaccessible I/O device by acting as a proxy, enabling data transmission and reception through a shared memory protocol, even if the primary processor cannot directly access the I/O device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a primary processor directly accesses I/O devices, then communication speed and system simplicity are improved, but electrical or logical incompatibilities prevent access to certain I/O devices

Engineering Contradiction:
Improvecommunication speedVSAvoidI/O device accessibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

A relay processor is introduced as an intermediary component between the primary processor and inaccessible I/O devices. The relay processor has direct electrical and logical access to specific I/O devices that the primary processor cannot reach, enabling the primary processor to communicate with these devices through the relay processor via shared memory, thereby expanding system adaptability without compromising communication efficiency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a relay processor is added to access inaccessible I/O devices, then I/O device accessibility is improved, but system complexity increases

Engineering Contradiction:
ImproveI/O device accessibilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system is segmented into distinct functional components: a primary processor handling main control functions and a relay processor handling specific I/O device communications. This segmentation allows each processor to be optimized for its specific role, with the relay processor dedicated to bridging compatibility gaps between the primary processor and legacy I/O devices, thereby managing system complexity through functional decomposition

Inventive Principle:
Principle #1Segmentation

3Device complexity

If direct communication between primary processor and I/O devices is used, then system simplicity is maintained, but communication capability with legacy devices is lost

Engineering Contradiction:
Improvesystem simplicityVSAvoidcommunication capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The relay processor creates a virtual communication interface that copies or emulates the I/O device protocols and communication methods. By implementing protocol translation and emulation capabilities, the relay processor allows the primary processor to communicate with legacy I/O devices using familiar communication patterns, maintaining system simplicity from the primary processor's perspective while ensuring reliable communication with diverse I/O devices

Inventive Principle:
Principle #26Copying

Data Source

PatentEP3411797B1Relay mechanism to facilitate processor communication with inaccessible input/output (i/o) device
Publication Date: 2023.09.13 HONEYWELL INTERNATIONAL INC
  • EP3411797B1 patent drawingFigure 1
  • EP3411797B1 patent drawingFigure 2
  • EP3411797B1 patent drawingFigure 3

AI summary

A method includes transmitting (404), by a first processing device (142, 148, 204), a signal to a second relay processing device (216, 326). The signal includes a message for the second relay processing device to transmit a read command and/or a write command to an I/O device (104a, 104b, 312) that is not accessible by the first processing device. The method also includes receiving (406), by the first processing device, an indication that the second relay processing device has transmitted the read command and/or the write command to the I/O device.