Released Fin Isolation for High Density IC Fabrication
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving high transistor density and maintaining device performance as feature sizes scale below the 10 nanometer node, particularly due to constraints in lithographic processes and the trade-off between feature dimension and spacing, which current fin isolation techniques fail to address effectively.
Innovation Solution
The approach involves performing fin release and gate aligned fin cut isolation after gate patterning, allowing for self-aligned gate electrodes and reduced dummy gate usage, thereby enabling more aggressive diffusion spacing and higher transistor density without increasing chip layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fin isolation techniques are used, then lithographic process constraints are reduced, but transistor density and device performance deteriorate due to the trade-off between feature dimension and spacing
Solution Approach 1:
The fin release and isolation structures are prepared in advance before gate patterning. Sacrificial layers are pre-formed beneath the fins, and isolation dielectric material is pre-deposited, allowing subsequent self-aligned processing that achieves high density without compromising dimensional control
Solution Approach 2:
The isolation structures are self-aligned to the gate electrodes through the self-aligned gate electrode formation process. The gate pattern itself defines the isolation regions, eliminating the need for separate alignment processes and enabling aggressive diffusion spacing while maintaining precise feature dimensions
2Productivity
If feature dimensions are reduced to increase transistor density, then chip capacity increases, but lithographic process constraints become overwhelming and device performance deteriorates
Solution Approach 1:
The invention transitions from planar isolation to three-dimensional self-aligned isolation where vertical profiles and lateral positioning are decoupled. The isolation structures extend vertically and are positioned laterally by the gate pattern, enabling aggressive diffusion spacing while maintaining device performance through precise spatial control in multiple dimensions
Solution Approach 2:
The method enables aggressive diffusion spacing parameters that would be impossible with conventional alignment. By changing the spacing parameter to be defined by gate width rather than separate alignment tolerances, the system achieves higher density while maintaining the critical dimension control needed for device performance
3Reliability
If more dummy gates are used to maintain isolation, then device performance is maintained, but chip layout area increases and transistor density decreases
Solution Approach 1:
The invention extracts and removes the need for dummy gates by implementing self-aligned isolation that provides adequate isolation for all functional gates. The isolation structures are formed only where needed based on the actual gate pattern, eliminating wasted space from dummy gates while maintaining performance
Data Source
AI summary
Released fins for advanced integrated circuit structure fabrication are described. For example, an integrated circuit structure includes a sub-fin. A dielectric spacer material is on the sub-fin. A fin is on the dielectric spacer material. A void in the dielectric spacer material, the void vertically between the sub-fin and the fin.