Releveled Bump Plane for Uniform Chiplet Bonding
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Solution Overview
Problem
The increasing complexity of microelectronic structures, particularly in 3D stacking, leads to uneven bump planes when bonding chiplets, which complicates the bonding process and requires a method to create a level surface for subsequent component attachment.
Innovation Solution
The method involves bonding chiplets to a chip using through silicon vias and patterning a photo resist layer to create openings for plating posts, followed by releveling the surface through planarization and applying a solder cap, ensuring a single level bump plane for further bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chiplets are bonded to a chip using through silicon vias, then interconnection functionality is improved, but the bump plane becomes uneven making subsequent bonding difficult
Solution Approach 1:
The patent applies preliminary action by performing releveling operations (planarization, epitaxial growth, or chemical mechanical polishing) on the bump plane after chiplet bonding but before subsequent component attachment. This intermediate releveling step prepares the surface in advance for the next bonding operation, ensuring uniformity is restored after the disruptive TSV bonding process.
Solution Approach 2:
The patent introduces intermediary processes (planarization layers, epitaxial growth layers, or CMP polishing) that act as mediators between the uneven bump plane created by TSV bonding and the requirements for uniform subsequent bonding surfaces. These intermediary steps transform the uneven surface into a level one without removing the functional TSV interconnections.
2Manufacturing precision
If multiple releveling steps are performed to create a uniform bump plane, then bonding consistency is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by selectively releveling only the bump plane region that requires uniformity for subsequent bonding, rather than processing the entire chip structure. This localized approach to planarization, epitaxial growth, or CMP polishing reduces overall process complexity while achieving the necessary uniformity where it is most critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient reconfiguration of the bump plane to a single level, facilitating consistent bonding and reducing complexity in 3D stacking by creating a uniform surface for subsequent layers, thereby enhancing the integration of advanced blocks like SerDes and memory chips.
Implementation Method 1
The uneven surface may then be prepared for releveling by patterning and exposing a first photo resist layer over the bonded chip and chiplets such that a plurality of openings are created in the photo resist layer exposing the through silicon via interconnects
Implementation Method 2
The patterning may be followed by plating a plurality of posts such that the posts are disposed in the openings
Implementation Method 3
The post may then be releveled such that the surface of the chip bonded with chiplets is reconfigured to be a single level
Data Source
AI summary
An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.