Relocatable BIST Elements for Mixed-Signal ASIC Testing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional testing methods for platform ASICs are costly and inefficient, as they require additional hardware and time to support mixed-signal functions, often relying on digital or analog-only testers.

Innovation Solution

A method and architecture for implementing relocatable built-in self-test (BIST) elements using a metal-programmable base layer of a platform ASIC, allowing for the instantiation of BIST functions alongside mixed-signal elements on a digital test flow without special testing or fixtures, utilizing pre-diffused regions and metal mask sets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional testing methods are used for mixed-signal functions, then testing capability is provided, but test time and hardware cost increase

Engineering Contradiction:
Improvetesting capabilityVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements built-in self-test (BIST) functionality where the mixed-signal device tests itself using on-chip test circuits. The BIST controller generates test patterns, applies them to the mixed-signal function, and captures results without external test equipment, enabling the device to perform self-diagnosis and reducing external testing requirements

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent creates a universal BIST architecture that can test multiple types of mixed-signal functions (ADC, DAC, PLL, voltage regulators, etc.) using a single standardized test interface. The relocatable BIST elements can be configured to test different functions through metal programming, eliminating the need for dedicated test circuits for each mixed-signal component

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional hardware is added to support mixed-signal testing, then testing capability is improved, but hardware cost increases

Engineering Contradiction:
Improvetesting capabilityVSAvoidhardware cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the BIST control logic, test pattern generation, and result capture functionality into integrated on-chip circuits that share resources with the main device functionality. The BIST controller uses the same digital test interface already present in the device, and test circuits are combined with functional circuits to minimize additional hardware

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent uses metal-programmable BIST elements that can be configured to replicate different test functions through programmable interconnects and logic. Instead of implementing separate hardwired test circuits for each mixed-signal function, the system uses reconfigurable logic that can be programmed to copy and adapt to various testing requirements

Inventive Principle:
Principle #26Copying

3Reliability

If analog-only testers are used for mixed-signal functions, then testing capability is provided, but test time and hardware cost increase

Engineering Contradiction:
Improvetesting capabilityVSAvoidtest flow simplicity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces a BIST controller as an intermediary that bridges the digital test interface and the analog mixed-signal functions. The controller translates digital test patterns into analog test signals, applies them to the mixed-signal function, and converts analog responses back to digital form for analysis by the digital tester, enabling digital-only testing equipment to test analog functions

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7373622B2Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements
Publication Date: 2008.05.13 BELL SEMICONDUCTOR LLC
  • US7373622B2 patent drawing
  • US7373622B2 patent drawing
  • US7373622B2 patent drawing

AI summary

An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.