Relocatable FPGA Modules via Regular Fabric Layout
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Solution Overview
Problem
Existing FPGA technologies face challenges in efficiently relocating modules without recompilation, as the precise matching of placement sites and routing wires is required, which can be time-consuming and resource-intensive, especially in designs with complex clock and reset net distributions.
Innovation Solution
The development of an FPGA fabric with a regular layout at a fine granularity and the implementation of network-on-chip (NoC) architecture facilitates the relocation of modules by allowing for identical patterns of placement sites and routing wires, enabling the movement of modules from one location to another without recompilation through software features that manage the movement and duplication of modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If precise matching of placement sites and routing wires is required for module relocation, then relocation accuracy is improved, but processing time and resource consumption increase
Solution Approach 1:
The FPGA fabric is segmented into regularly spaced clusters with identical internal structures. Each cluster contains the same arrangement of placement sites and routing wires, allowing modules to be relocated between clusters without requiring complex rematching. This segmentation enables rapid relocation by simply copying module data to equivalent positions in target clusters, dramatically reducing processing time while maintaining relocation accuracy.
Solution Approach 2:
The patent changes the structural parameters of the FPGA fabric to create a regular, repeating pattern of clusters. By standardizing the layout parameters (spacing, orientation, resource distribution) across all clusters, the system enables parameter-based relocation where modules can be moved to any cluster position using simple coordinate transformation, avoiding time-consuming manual matching while preserving precise connectivity.
2Productivity
If regular layout at fine granularity is implemented, then module relocation efficiency is improved, but device complexity increases
Solution Approach 1:
Each cluster in the FPGA fabric is designed as a universal building block that can serve multiple functions and host different module types. The identical structure within each cluster allows any module placed in one cluster to be relocated to any other cluster without modification. This universality simplifies the overall fabric design by repeating a single proven template, reducing the effective complexity despite the fine-grained regular layout.
Solution Approach 2:
The FPGA fabric employs a nested hierarchical structure where identical smaller clusters are nested within larger regular patterns. This self-similar nesting allows the complex fine-grained layout to be managed through recursive application of the same cluster template, making the complexity systematic rather than chaotic. Software tools can efficiently handle this nested structure by operating at multiple levels of abstraction.
3Loss of time
If modules are relocated without recompilation, then processing time is reduced, but routing wire matching difficulty increases
Solution Approach 1:
The patent implements a copying mechanism where module placement and routing data from source clusters is directly copied to target clusters. Because all clusters have identical internal structures with the same wire patterns and connection points, the copied data automatically matches the target location without requiring recompilation or rematching. This copying approach eliminates time-consuming recompilation while simplifying wire matching through structural equivalence.
Data Source
AI summary
A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.