Relocated Parity Syndrome Checking for FPGA Configuration Frames
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Solution Overview
Problem
Existing error detection and correction methods for bitstream frames transmitted one word at a time in programmable logic devices, such as FPGAs, are inadequate for reliable error checking and correction, particularly in configurations exceeding a thousand bits, where single-bit errors can be corrected but double-bit errors cannot.
Innovation Solution
A method and apparatus for decoding encoded information that computes partial syndrome values for each word of a bitstream frame, combining them with previously stored syndromes, and using a feedback filter to manage syndrome values, enabling effective error detection and correction in programmable logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error checking methods are used for bitstream frames transmitted one word at a time, then the system can detect errors in transmitted data, but the error detection and correction capability is insufficient for configurations exceeding a thousand bits
Solution Approach 1:
The patent divides the bitstream frame into multiple words and processes them sequentially one word at a time. Each word is error-checked independently through syndrome computation, allowing the system to handle large configurations exceeding a thousand bits by breaking them into manageable segments that can be processed in sequence rather than requiring simultaneous processing of the entire frame.
Solution Approach 2:
The patent implements a feedback mechanism where syndrome values computed from received words are fed back into the system to determine whether errors are present. The syndrome logic uses these feedback values to identify and correct single-bit errors and detect double-bit errors, enabling reliable error checking without requiring complex external error checking hardware.
2Reliability
If parity bits are transmitted with data bits for error checking, then error detection and correction can be performed, but the method is inadequate for reliable error checking in large bitstream frames
Solution Approach 1:
The patent segments the bitstream frame into multiple words with associated parity bits, allowing each word to be error-checked independently. This segmentation enables the system to maintain data integrity for large configurations by processing smaller units sequentially, making error checking more manageable and reliable compared to treating the entire frame as a single unit.
Solution Approach 2:
The patent enables the data words and parity bits to perform error detection and correction themselves through syndrome computation. Each word carries its own error checking information, allowing the system to autonomously detect and correct errors without requiring external error checking mechanisms, thereby improving ease of operation while maintaining high reliability.
3Productivity
If bitstream frames are read one word at a time, then the transmission can be processed sequentially, but conventional error checking cannot reliably detect and correct errors in frames exceeding a thousand bits
Solution Approach 1:
The patent segments the bitstream frame into multiple words that are processed sequentially one at a time. This segmentation allows the system to maintain processing efficiency by reading and error-checking words in sequence rather than requiring the entire frame to be loaded simultaneously, while still achieving reliable error detection and correction for large frames exceeding a thousand bits through cumulative syndrome computation.
Solution Approach 2:
The patent maintains continuous error checking throughout the sequential processing of words by continuously computing and updating syndrome values as each word is received. This continuous action ensures that error detection and correction are performed reliably throughout the entire transmission process, preventing errors from accumulating undetected while maintaining high processing efficiency through sequential operation.
Data Source
AI summary
Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.