Remote Clock Distribution with Symmetric Phase Delay Compensation
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Solution Overview
Problem
In digital signal processing systems, distributing a clock signal across remote electronic subsystems leads to issues like data signals racing against the clock signal, causing design errors, and results in reduced clock frequency due to travel delays, making it challenging to ensure synchronized operation across multiple clock domains.
Innovation Solution
A method involving a learning period where a training signal is used to measure and adjust the phase delay in a bidirectional signal path, ensuring the clock signal has the same phase across subsystems, using phase locked loops to maintain symmetry and compensate for time delays, allowing the clock signals to be in phase despite differences in clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock signal is transmitted across remote electronic subsystems via bidirectional signal paths, then data transmission between subsystems is enabled, but clock signal phase differences and timing errors occur due to travel delays
Solution Approach 1:
The patent applies preliminary action by performing a learning period before normal operation, during which training signals are transmitted to measure and characterize the signal path delays. This advance measurement allows the system to pre-determine phase adjustment values that will be applied during actual clock signal distribution, eliminating timing errors before they occur in normal operation.
Solution Approach 2:
The patent implements feedback by transmitting training signals through the bidirectional signal path and measuring the actual travel time and phase differences. This measured information is fed back to the clock generator, which then adjusts its output clock signal phase accordingly. This closed-loop feedback mechanism continuously compensates for path delays and maintains synchronized operation across remote subsystems.
2Productivity
If clock frequency is increased to improve processing speed, then productivity increases, but timing synchronization errors worsen due to accumulated phase differences over longer clock periods
Solution Approach 1:
The patent applies dynamics by making the clock signal phase adjustable and adaptive rather than fixed. The clock generator dynamically adjusts the phase of distributed clock signals based on measured path delays and operational conditions. This dynamic phase adjustment allows the system to maintain precise timing synchronization even at higher clock frequencies where phase differences would otherwise accumulate and cause synchronization errors.
3Measurement precision
If individual clock synthesis is performed for each subsystem, then local clock timing precision is improved, but system complexity increases due to multiple clock sources requiring coordination
Solution Approach 1:
The patent introduces an intermediary approach where a single master clock generator serves as the primary time reference, and phase adjustment mechanisms act as intermediaries to distribute synchronized clock signals to all subsystems. This eliminates the need for each subsystem to independently synthesize clocks, thereby reducing system complexity while maintaining precise timing through the intermediary phase adjustment stage that compensates for transmission delays.
4Device complexity
If data transmission lines and clock lines share the same bidirectional path, then device complexity is reduced, but harmful interference occurs when data signals race against clock signals
Solution Approach 1:
The patent applies preliminary action by transmitting training signals through the shared bidirectional path before normal data transmission begins. This advance characterization of the signal path allows the system to determine the exact travel time and phase relationship between clock and data signals. Based on this preliminary measurement, the clock generator pre-adjusts the clock signal phase to account for the path delay, ensuring that clock edges arrive at the correct time even when sharing the path with data signals, thereby preventing racing conditions.
Solution Approach 2:
The patent implements preliminary anti-action by proactively adjusting the clock signal phase in opposition to the expected data signal travel delay. Before normal operation, the system measures the path characteristics and applies a counteracting phase shift to the clock signal. This preliminary anti-action prevents the harmful racing effect from occurring in the first place, as the clock signal is already compensated for the delay that would otherwise cause it to arrive too early or too late relative to data signals on the shared path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that clock signals have the same frequency and phase across all subsystems, reducing design errors and increasing the possible clock frequency, simplifying the design process by maintaining synchronized operation and eliminating the need for individual clock synthesis for each subsystem.
Implementation Method 1
using phase locked loops to maintain symmetry and compensate for time delays
Data Source
AI summary
A clock signal from a first electronic subsystem is distributed to a second electronic subsystem. The second electronic subsystem is remote from the first electronic subsystem and coupled to the first electronic subsystem by a bidirectional signal path. A first clock signal is generated on the first electronic subsystem and a training signal is generated on the first electronic subsystem clocked by the first clock signal. The training signal is sent on the bidirectional signal path on a round trip to the second electronic subsystem and back to the first electronic subsystem. A phase of the training signal is adjusted symmetrically on the way to the second electronic subsystem in a first phase adjuster and on the way back to the first electronic subsystem in a second phase adjuster until the measured time for the round trip is equal to an even number of clock cycles.