Remote Clock Synchronization Using Three Phase Measurements
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Solution Overview
Problem
Existing synchronization methods for device clocks with remote target clocks in wireless communication systems, such as NFC, require long locking times and continuous operation, leading to increased power consumption and potential disturbances.
Innovation Solution
A synchronization method involving time measurement means to determine phase differences, frequency correction means to adjust the device clock frequency, and phase correction means to synchronize the device clock with the target clock, requiring only three measurements and reducing continuous operation, thereby minimizing power consumption and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuous synchronization operation is used to maintain clock synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic synchronization measurements instead of continuous operation. The system performs measurements at specific intervals (e.g., when needed for communication sessions) rather than continuously, thereby maintaining synchronization accuracy when required while significantly reducing power consumption during idle periods.
2Measurement precision
If traditional phase lock loop circuits are used for synchronization, then clock synchronization is achieved, but locking time is extended
Solution Approach 1:
The patent performs preliminary rough alignment of clock phases before fine synchronization. By pre-positioning the clocks close to each other using lower-precision methods or initial estimates, the subsequent high-precision phase lock loop operation requires fewer adjustments and converges faster, thereby reducing overall locking time while maintaining synchronization accuracy.
3Measurement precision
If continuous synchronization measurements are performed to maintain accuracy, then phase and frequency alignment is improved, but device complexity increases
Solution Approach 1:
The patent divides the synchronization process into distinct segments: initial clock extraction, rough phase alignment, fine frequency synchronization, and periodic maintenance measurements. Each segment uses appropriately scaled measurement techniques, avoiding the need for continuously high-precision measurements and reducing overall system complexity while maintaining adequate alignment accuracy.
Data Source
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AI summary
A device (1)) with an antenna that receives a target carrier signal (3) from a remote target (2) and transmits a device carrier signal (6) modulated with data to communicate data between the device (1) and the target (2), which device (1) comprises: clock extraction means (4) to extract a target clock (5) from the target carrier signal (3); driver means (9) to generate the device carrier signal (6) from a device clock (8); synchronization means (7) to synchronize the frequency and phase of the device clock (8) with the target clock (5), wherein that the synchronization means (7) comprise: time measurement means (10) to measure the phase difference between the target clock (5) and the device clock (8) or an internal device clock (33) related to the device clock (8) and to provide a phase information (ϕ1, ϕ2 , ϕ3); measurement control means (20) to initiate a first time measurement that results in a first phase information (ϕ1) and to initiate a second time measurement a fixed time period (ΔT) after the first time measurement that results in a second phase information (ϕ2); frequency correction means (11) to correct the frequency of the device clock (8) and/or the internal device clock (33) to the frequency of the target clock (5) based on an evaluation of the first phase information (ϕ1) and second phase information (ϕ2) by evaluation means (21); which measurement control means (20) are built to initiate a third time measurement after the frequency correction of the device clock (8) and/or the internal device clock (33) that results in a third phase information (ϕ3) evaluated by the evaluation means (21) and corrected by phase correction means (22) which correct the phase of the device clock (8) to the phase of the target clock (5).