Remote Core Operations in Multi-Core Processors
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Solution Overview
Problem
Multi-core processors with shared physical memory face challenges in maintaining cache coherency, which is computationally expensive and resource-intensive, affecting performance and power usage.
Innovation Solution
A method where a sending core sends a memory write request to a destination core, using a shared data structure as a message channel, eliminating the need for cache coherency mechanisms by ensuring up-to-date data visibility without relying on cache coherency protocols, and implementing a notification mechanism using shared physical memory to notify destination cores of events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherency protocols are used to maintain data consistency across cores, then data visibility is ensured, but computational overhead and interconnect resource usage increase
Solution Approach 1:
The patent extracts the coherency maintenance responsibility from the hardware cache coherency protocol and relocates it to the software layer. Each core maintains its own cache independently without hardware-enforced coherency, and software (operating system or application) is responsible for managing data consistency through explicit synchronization primitives and memory barriers.
Solution Approach 2:
The patent introduces software synchronization primitives (locks, semaphores, memory barriers) as intermediaries between cores to coordinate access to shared data. These software-based mediators replace the need for complex hardware coherency protocols by providing explicit control over when data is read, written, and synchronized across cores.
2Adaptability or versatility
If shared physical memory is used for inter-core communication, then data sharing is enabled, but cache coherency overhead increases power consumption
Solution Approach 1:
The patent removes the power-intensive hardware cache coherency protocol from the system and transfers the responsibility to software. This extraction eliminates the continuous monitoring and invalidation signals that hardware coherency protocols generate, significantly reducing interconnect traffic and power consumption while maintaining shared memory functionality.
Solution Approach 2:
Instead of continuous hardware monitoring of cache states, the patent employs periodic software-based synchronization where cores explicitly signal when they need to access or modify shared data. This periodic action reduces the frequency of coherence checks and associated power consumption while maintaining data consistency when needed.
3Reliability
If hardware cache coherency mechanisms are implemented, then data visibility is maintained, but interconnect resources are consumed
Solution Approach 1:
The patent extracts the coherency management function from hardware interconnect resources and implements it in software. This eliminates the need for dedicated coherency interconnect channels, invalidation messages, and hardware arbitration logic, freeing up significant interconnect bandwidth for actual data communication between cores.
Solution Approach 2:
Each core independently manages its own cache contents without relying on hardware-mediated coherency protocols. Cores use software synchronization primitives to self-coordinate access to shared memory, eliminating the need for interconnect resources dedicated to coherency maintenance while preserving data visibility through explicit software control.
Data Source
AI summary
A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.