Remote DSB Filtering for Low-Latency TLB Invalidation
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Solution Overview
Problem
Conventional processor-based devices incur significant latency and performance degradation due to the unnecessary execution of Data Synchronization Barrier (DSB) instructions across multiple processors, which are triggered by TLB invalidation operations, leading to resource wastage and inefficiency.
Innovation Solution
Implementing a DSB filter circuit in remote processors to determine whether TLB invalidation instructions satisfy filtering criteria, allowing the processors to forego unnecessary DSB operations and issue early acknowledgments, thereby conserving resources and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DSB instructions are broadcast to all remote processors to ensure TLB translation consistency, then memory request completion is guaranteed, but processor resources are wasted and latency increases
Solution Approach 1:
The patent applies local quality by making each remote processor's response to DSB instructions local and selective rather than universal. The DSB filter circuit locally determines whether a specific remote processor needs to execute the DSB operation based on whether it has cached translations for the invalidated TLB entry, allowing only necessary processors to perform the synchronization operation.
Solution Approach 2:
The patent implements partial action by having remote processors selectively execute DSB operations only when necessary. Instead of requiring all remote processors to unconditionally execute DSB instructions, the system performs the minimum necessary synchronization actions - only those processors with cached translations for the invalidated entry execute DSB, avoiding excessive synchronization overhead.
2Reliability
If DSB instructions are executed by all remote processors, then memory request completion is ensured, but TLB invalidation latency increases
Solution Approach 1:
The DSB filter circuit enables local quality by allowing each remote processor to independently determine its need for DSB execution based on its local TLB state. This localized decision-making eliminates unnecessary waiting and synchronization delays at processors that don't require the operation, thereby reducing overall TLB invalidation latency while maintaining reliability.
Solution Approach 2:
The patent applies preliminary action through the DSB filter circuit, which预先 (in advance) determines whether a remote processor needs to execute the DSB operation before the actual DSB execution. This preliminary filtering prevents unnecessary processing delays and allows the system to proceed with TLB invalidation at optimal speed while ensuring memory request completion where needed.
3Reliability
If DSB operations are executed by remote processors, then translation consistency is maintained, but system performance degrades
Solution Approach 1:
The patent implements local quality by enabling each remote processor to independently assess its translation cache state and selectively execute DSB operations only when necessary. The DSB filter circuit provides local intelligence that maintains translation consistency only where required, avoiding the performance penalty of universal DSB execution across all remote processors.
Solution Approach 2:
The system performs partial DSB execution - only the subset of remote processors that actually have cached translations for the invalidated TLB entry execute the DSB operation. This partial action approach maintains translation consistency for affected translations while avoiding the excessive performance degradation that would result from requiring all remote processors to execute unnecessary DSB operations.
Data Source
AI summary
Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.