Remote Hit Predictor for Speculative Probe Latency

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Solution Overview

Problem

In computer systems, cache coherence mechanisms increase latency due to overhead in maintaining coherence states and communication among caches, especially in multiprocessor systems with point-to-point interconnects, where stale data issues and write order inconsistencies arise.

Innovation Solution

Implementing a remote hit predictor in each node to speculate which node has a coherent copy of a memory block, allowing for a speculative probe to be sent directly to that node, potentially reducing latency by bypassing the traditional three-hop protocol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional cache coherence protocols are used in multiprocessor systems with point-to-point interconnects, then cache coherence is maintained, but memory request latency increases due to multiple communication hops and overhead

Engineering Contradiction:
Improvecache coherenceVSAvoidmemory request latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by having each node maintain a remote hit predictor that pre-speculates which remote node holds a coherent copy of a memory block before an actual memory request arrives. When a memory request comes in, the node controller checks the predictor and can immediately issue a speculative probe to the predicted node, bypassing the traditional multi-hop coherence protocol. This preliminary prediction and preparation of probe paths reduces the latency penalty while maintaining coherence guarantees.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The remote hit predictor acts as an intermediary structure that mediates between the memory requestor and the actual data holder. Instead of directly implementing the complex coherence protocol through multiple hops, the predictor provides a simplified path by identifying the likely data location in advance, allowing the system to bypass intermediate coherence check nodes and reduce communication overhead.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If writeback cache is used to reduce memory bandwidth consumption, then write operations are delayed in cache, but stale data issues arise when multiple producers write to the same memory location

Engineering Contradiction:
Improvememory bandwidth consumptionVSAvoiddata consistency
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements feedback through the remote hit predictor, which learns from actual cache hit patterns and update sequences to improve its predictions. When a node receives probe responses or memory updates, this information feeds back into the predictor to refine its speculation about which nodes hold coherent copies. This feedback mechanism ensures that even with delayed writeback operations, the system maintains data consistency by accurately tracking where stale or updated data resides.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7640401B2Remote hit predictor
Publication Date: 2009.12.29 ADVANCED MICRO DEVICES INC
  • US7640401B2 patent drawing
  • US7640401B2 patent drawing
  • US7640401B2 patent drawing

AI summary

In one embodiment, a first node comprises at least one memory request source and a node controller coupled to the memory request source. The node controller comprises a remote hit predictor configured to predict a second node to have a coherent copy of a block addressed by a memory request generated by the memory request source, and the node controller is configured to issued a speculative probe to the second node responsive to the prediction and to the memory request.