Remote I/O Variation Detection Circuit
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Solution Overview
Problem
Conventional remote I/O systems experience prolonged data transfer times due to CPU processing requirements, leading to undesirable waiting times in data transfer between the information network control module and the I/O interface module, which affects the overall data transfer speed and efficiency.
Innovation Solution
The implementation of a variation detecting circuit within the information network control module that compares data in a data latch buffer with a variation detection memory to detect changes, allowing for cyclic scan transmission without CPU processing, thereby reducing data transfer time and eliminating the need for CPU processing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPU processing is used to designate scan memory areas for data transfer, then data transfer control is achieved, but data transfer time increases
Solution Approach 1:
The patent extracts the CPU from the data transfer path by implementing a cyclic scan mechanism that operates autonomously. The CPU only designates scan memory areas once, then the system automatically cycles through these areas without further CPU intervention, eliminating continuous CPU processing delays while maintaining reliable data transfer control.
Solution Approach 2:
The CPU performs preliminary action by designating scan memory areas in advance. Once the scan memory areas are designated, the system executes automatic cyclic scanning without requiring further CPU involvement. This preliminary setup enables subsequent data transfers to proceed without CPU processing delays.
2Productivity
If batch input/output processing is implemented for concurrent data transfer, then data transfer efficiency improves, but waiting time occurs due to CPU processing requirements
Solution Approach 1:
The patent implements continuous useful action through automatic cyclic scanning of designated memory areas. Once the CPU designates the scan memory areas, the system continuously cycles through them without interruption or waiting for CPU processing, maintaining constant data transfer efficiency without periodic waiting times.
Solution Approach 2:
The system performs self-service by automatically scanning designated memory areas without requiring continuous CPU intervention. The cyclic scan mechanism serves itself by autonomously managing data transfer between I/O interface modules and remote I/O modules, eliminating waiting time caused by CPU processing requirements.
3Measurement precision
If CPU processing is required for each data transfer operation, then data transfer accuracy is maintained, but overall data transfer speed decreases
Solution Approach 1:
The patent segments the data transfer process into two distinct phases: an initial CPU setup phase where scan memory areas are designated with precise control, and a subsequent automatic cyclic scan phase that maintains accuracy through predefined scanning sequences. This segmentation allows high-speed automatic scanning while preserving data transfer accuracy established during the initial CPU-controlled phase.
Data Source
AI summary
A remote I/O system includes an information network control module, I/O interface modules, and a remote I/O module. The information network control module includes a common memory and a second control IC. The second control IC includes a variation detecting circuit that includes a data latch buffer that stores read data from an information network; and a variation detection memory that stores data previously read from the information network. The variation detecting circuit compares data stored in the data latch buffer with data stored in the variation detection memory, to detect a variation in the data. The second control IC transmits, to the I/O interface module, by cyclic scan transmission, data from one of the scan memory areas corresponding to the data having the variation detected by the variation detecting circuit.