Remote Memory Controller for Low Latency PCIe Access
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Solution Overview
Problem
Current memory replication methods between computing devices, especially those using PCIe interconnects, face significant latency issues and security concerns, particularly when dealing with high-speed non-volatile memory (NVRAM), leading to performance bottlenecks and potential system failures due to network security vulnerabilities and inefficient data packetization.
Innovation Solution
The implementation of a system and method that utilizes a remote memory controller to manage memory access requests through a PCIe interconnect, employing a security key and unique identifier to authorize access, allowing for low-latency reading and writing of memory while preventing unauthorized access and optimizing data transfer by using DMA operations and buffering data in separate chunks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-transparent bridging (NTB) on PCIe connection is used to enable high-speed memory replication, then memory access speed is improved, but security vulnerabilities and system stability deteriorate due to inability to safeguard against unauthorized memory access and system corruption
Solution Approach 1:
The patent introduces a remote memory controller as an intermediary device between the initiator and target computing devices. This controller receives memory access requests, verifies security credentials (security keys and unique identifiers), and manages data transfer between NVRAM and system memory. By positioning this trusted intermediary in the data path, the system maintains high-speed access while preventing unauthorized memory operations and system corruption that would occur with direct NTB connections.
2Adaptability or versatility
If data is broken into 16-byte packets for PCIe transfer, then compatibility with current processors is improved, but transfer efficiency and latency deteriorate due to poor utilization of PCIe bandwidth
Solution Approach 1:
The patent segments the data transfer process into two distinct phases: first, large blocks of data (up to 4096 bytes) are transferred efficiently over the PCIe interconnect using optimized packetization; second, the remote memory controller performs internal buffering and reassembly of these data blocks before writing to NVRAM. This segmentation allows the system to exploit large PCIe payload sizes for high-speed transfer while managing the complexity of variable-sized NVRAM writes through controlled segmentation at the controller level.
Solution Approach 2:
The patent changes the dimension of data organization by introducing a new layer of abstraction between PCIe data packets and NVRAM storage operations. Instead of directly mapping 16-byte processor packets to NVRAM, the system operates in a different dimensional space where data is organized into large PCIe payloads (4096 bytes) that are then managed by the remote memory controller through buffering and reassembly, effectively adding a temporal and organizational dimension to the data transfer process.
3Reliability
If synchronous replication is used to achieve zero-loss high availability, then data reliability is improved, but performance deteriorates due to the bottleneck created by slower storage systems
Solution Approach 1:
The patent fundamentally changes the storage medium parameter from traditional synchronous replication using slower storage systems to synchronous replication using high-speed NVRAM. By altering the physical characteristics of the storage medium (from disk-based or flash-based storage to NVRAM), the system achieves both zero-loss data availability through synchronous replication and high performance through the superior speed characteristics of NVRAM, which can execute read and write commands significantly faster than conventional storage.
Data Source
AI summary
Disclosed are methods and systems for low latency modification of memory on a remote computer system. According to one aspect of the present disclosure, a method includes, at a first computing device, receiving from a second computing device, a memory access request including a security key and a unique identifier generated by the first computing device. The method further includes verifying, based on the security key and the unique identifier, that the first computing device is authorized to access a predetermined portion of memory. Also, in response to verifying that the first computing device is authorized to access the predetermined portion of memory, accessing, by the second computing device, the predetermined portion of memory.