Remote Memory Synchronization Merging for Low-Latency Data Transfer

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Solution Overview

Problem

Existing remote memory operations in multiprocessor systems suffer from significant latency and inefficiency due to the use of low-performance interconnects and the need for explicit memory synchronization operations, which are costly and complex, especially when transferring small data blocks.

Innovation Solution

The method involves merging a memory store operation with a synchronization operation to create a self-synchronizing memory store operation, which is transmitted as a single unit and split at a point of consistency near the destination, allowing the memory operation to execute before the synchronization operation, thereby reducing network latency and bandwidth overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If explicit memory synchronization operations are used for remote memory operations, then data transfer reliability is ensured, but network latency and bandwidth overhead increase significantly

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidnetwork latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines the memory store operation and synchronization operation into a single unified operation. The source processing unit issues one operation that performs both the data transfer and synchronization functions, eliminating the need for separate synchronization operations over the network. This merging reduces the number of network round-trips and associated latency while maintaining data transfer reliability through the atomic nature of the combined operation.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multiple separate operations (memory store, synchronization, acknowledgement) are performed over the interconnect, then data transfer correctness is maintained, but device complexity and operational overhead increase

Engineering Contradiction:
Improvedata transfer correctnessVSAvoidoperational overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple separate operations (memory store, synchronization, and acknowledgement) into a single unified operation. The destination processing unit receives one operation that encompasses all three functions, processes them atomically, and returns a single completion indication. This eliminates the complexity of coordinating multiple separate operations, reducing protocol overhead and simplifying the interconnect communication.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If small data blocks are transferred using traditional remote memory operations, then data transfer flexibility is maintained, but the overhead of synchronization operations becomes disproportionately high

Engineering Contradiction:
Improvedata transfer flexibilityVSAvoidtransfer efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent combines the memory store and synchronization operations into a single operation, which eliminates the disproportionate overhead of separate synchronization operations for small data blocks. By issuing one unified operation instead of multiple separate operations, the patent maintains flexibility in transferring data blocks of any size while significantly improving efficiency, as the synchronization overhead is now embedded within the data transfer operation itself rather than being additive.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12517730B2Self-synchronizing remote memory operations in a data center or multiprocessor system
Publication Date: 2026.01.06 NVIDIA CORP
  • US12517730B2 patent drawing
  • US12517730B2 patent drawing
  • US12517730B2 patent drawing

AI summary

Various embodiments include techniques for performing self-synchronizing remote memory operations in a data center or multiprocessor computing system. During a remote memory operation, a source processor transmits multiple data segments to a destination processor. For each data segment, the source processor transmits a remote memory operation to the destination processor that includes associated metadata that identifies the memory location of a corresponding synchronization object representing a count of data segments to be stored or a flag for each data segment to be stored. The remote memory operation along with the metadata is transmitted as a single unit to the destination processor. The destination processor splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processor avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.