Remote Permission Invalidation for Cross-Processor Memory Access
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Solution Overview
Problem
Existing processor systems lack efficient mechanisms to securely and fine-grainedly invalidate memory permission information across different processors, leading to potential security vulnerabilities and inconsistencies in memory access permissions.
Innovation Solution
A primary processor executes a remote permission table invalidate instruction to directly update and invalidate secondary processor's permission information, ensuring secure and fine-grained control by using both page table and secure access permission table caching, with acknowledgement and power management to ensure efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor caches permission information locally for fast access, then memory access speed is improved, but permission consistency across multiple processors deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the first processor monitors permission changes in its page tables and automatically invalidates corresponding cached permission information in the second processor's translation lookaside buffer (TLB). This ensures that when the first processor updates permission bits for a memory page, the second processor is notified and invalidates its cached permission data, maintaining consistency across processors while allowing caching for performance.
2Reliability
If fine-grained permission control is implemented across processors, then security is improved, but system complexity deteriorates
Solution Approach 1:
The patent segments permission control into distinct components: the first processor maintains authoritative page table permission information, while the second processor caches this information in its TLB for fast access. The invalidation mechanism is segmented to target specific TLB entries based on virtual address mappings, allowing fine-grained control without requiring complex global synchronization. This segmentation enables secure multi-processor operation by clearly defining roles and responsibilities for permission management.
3Loss of time
If permission information is invalidated remotely across processors, then permission updates are timely, but communication overhead increases
Solution Approach 1:
The patent applies local quality by making the invalidation mechanism targeted and selective rather than broadcast to all processors. When the first processor invalidates permission information, it provides specific identifiers (such as virtual address ranges or TLB entry tags) that allow the second processor to invalidate only the relevant cached entries. This localized approach minimizes unnecessary communication and processing overhead while ensuring timely invalidation of affected permission data.
Data Source
AI summary
Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.