Remote Permission Invalidation for Cross-Processor Memory Access
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Solution Overview
Problem
Existing processor systems lack efficient mechanisms to securely and fine-grainedly invalidate memory permission information across different processors, leading to potential security vulnerabilities and inconsistencies in memory access permissions.
Innovation Solution
A primary processor executes a remote permission table invalidate instruction to directly update and invalidate secondary processor's permission information, ensuring secure and fine-grained control by using both page table and secure access permission tables, even in low-power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a processor caches permission information locally for fast access, then access speed improves, but permission consistency and security across multiple processors deteriorate
Solution Approach 1:
The system proactively invalidates cached permission information in the secondary processor before actual memory access occurs. When the primary processor updates permission bits in the page table or secure access permission table, it sends an invalidate command to the secondary processor to clear its cached permission information, ensuring that stale permission data does not compromise security.
Solution Approach 2:
The primary processor monitors and controls the permission information in the secondary processor's cache. When permission bits are updated in the primary processor's page table or secure access permission table, feedback is sent to the secondary processor to invalidate its cached permission data, maintaining synchronization between processors.
2Reliability
If permission information is updated frequently to maintain security, then security improves, but system performance and access efficiency deteriorate
Solution Approach 1:
The invalidation mechanism operates at a fine-grained level, targeting only specific permission information entries that need updating. The primary processor can invalidate individual page table entries or secure access permission table entries in the secondary processor's cache, rather than forcing a complete cache flush, thus maintaining security while minimizing performance impact.
Solution Approach 2:
The system performs selective invalidation of only the necessary permission information entries in the secondary processor's cache, rather than invalidating the entire cache. This partial action approach maintains security for updated entries while preserving cached data for other entries, avoiding unnecessary performance degradation.
3Reliability
If the primary processor maintains full control over permission information, then security control improves, but device complexity and communication overhead worsen
Solution Approach 1:
The patent introduces an intermediary invalidation command mechanism between the primary and secondary processors. The primary processor sends targeted invalidate commands to the secondary processor's cache, which handles the actual invalidation of permission information locally. This intermediary approach maintains security control while reducing the complexity of direct continuous monitoring and updating.
Data Source
AI summary
Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes secondary processor permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the secondary processor permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.