Remote Register Updates for DPDK Latency Reduction
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Solution Overview
Problem
The Data Plane Development Kit (DPDK) experiences performance degradation due to frequent context switching between user and kernel spaces for power management operations, leading to latency and potential failure in meeting performance requirements, especially during high-speed packet processing.
Innovation Solution
A mechanism where one core measures and encrypts packet processing activity and operating parameters, allowing another core to access and modify these parameters securely without interrupting the packet processing, using a shared register space and secure key for authorized access, thus decoupling the data and management planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power management operations are performed on the same core as DPDK packet processing, then secure access to PMU registers is achieved, but context switching between user and kernel spaces causes performance degradation and latency
Solution Approach 1:
The system divides the CPU into multiple cores: one core (first core) is dedicated to DPDK packet processing in user space, while another core (second core) handles power management operations in kernel space. This segmentation allows both functions to operate simultaneously without context switching, resolving the contradiction between secure PMU register access and packet processing performance.
Solution Approach 2:
A shared memory region acts as an intermediary between the first core and second core. The first core writes performance measurement data to this shared memory, and the second core reads from it to make power management decisions. This intermediary mechanism enables communication between cores without requiring context switches, maintaining high packet processing performance while achieving secure power management.
2Use of energy by stationary object
If the DPDK process sleeps to free up the CPU during low activity, then power consumption is reduced, but packet processing delays occur when packets are received during sleep period
Solution Approach 1:
The system implements feedback through performance monitoring units (PMUs) that continuously measure packet processing activity and write results to shared memory. The power management process on the second core reads these measurements and dynamically adjusts CPU frequency and power states based on actual traffic conditions. This feedback mechanism allows the system to reduce power consumption during low activity without causing packet processing delays, as the PMU continuously monitors for activity and can trigger wake-up events.
Data Source
AI summary
Examples described herein provide for a first core to map a measurement of packet processing activity and operating parameters so that a second core can access the measurement of packet processing activity and potentially modify an operating parameter of the first core. The second core can modify operating parameters of the first core based on the measurement of packet processing activity. The first and second cores can be provisioned on start-up with a common key. The first and second cores can use the common key to encrypt or decrypt measurement of packet processing activity and operating parameters that are shared between the first and second cores. Accordingly, operating parameters of the first core can be modified by a different core while providing for secure modification of operating parameters.