Remote TLB and PTW Circuitry for Address Translation
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Solution Overview
Problem
Existing systems face challenges in efficiently translating virtual addresses to physical addresses in hyper-sparse graph workflows, leading to suboptimal performance in network and memory bandwidth utilization.
Innovation Solution
Implementing a remote TLB and PTW circuitry at each memory endpoint to perform virtual-to-physical translations locally, reducing the need for translations to be sent back to the issuing core, and using indirect load/store operations to enhance efficiency in graph algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If virtual-to-physical address translations are performed centrally at the issuing core, then address translation consistency is maintained, but translation latency increases and bandwidth utilization decreases
Solution Approach 1:
The patent divides the centralized address translation function into distributed segments across multiple memory endpoints. Each memory endpoint maintains its own translation lookaside buffer (TLB) and page table walker (PTW) circuitry, allowing local translation of virtual addresses without requiring centralized processing at the issuing core. This segmentation reduces translation latency and improves bandwidth utilization while maintaining translation consistency through coordinated management protocols.
2Loss of time
If remote TLB and PTW circuitry is implemented at each memory endpoint, then translation latency is reduced, but hardware complexity at each endpoint increases
Solution Approach 1:
The patent merges the translation lookaside buffer (TLB) and page table walker (PTW) circuitry directly into each memory endpoint's existing hardware structure. By integrating these translation functions with the memory controller and address decoding logic already present at each endpoint, the design reduces translation latency without proportionally increasing overall system complexity. The merged architecture allows local address translation to occur in parallel with memory access operations.
3Productivity
If translations are performed locally at memory endpoints, then network and memory bandwidth utilization improves, but consistency management complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where memory endpoints report translation status and page table walk results back to the issuing core or a centralized translation management unit. This feedback loop enables coordinated management of distributed translations, ensuring consistency across the system while allowing local endpoints to perform translations independently. The feedback protocol allows for invalidation, synchronization, and error handling without requiring constant centralized control of each translation operation.
Data Source
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AI summary
Apparatus and method for remote virtual-to-physical address translations. For example, one embodiment of a processor comprises: an interconnect network; a plurality of cores coupled to the interconnect network, a core of the plurality of cores comprising a core translation lookaside buffer (TLB) and core page table walk (PTW) circuitry; a plurality of memory endpoint subsystems coupled to the interconnect network, each memory endpoint subsystem comprising a memory access circuit and a memory to be accessed via the interconnect network, each memory access circuit comprising a memory endpoint TLB and memory endpoint PTW circuitry; wherein one or more of the memory endpoint subsystems are to perform operations to process an indirect memory access request on behalf of a requesting core, the one or more of the memory endpoint subsystems to: read a virtual pointer address based on the indirect memory access request, translate the virtual pointer address to a physical pointer address, access data based on the physical pointer address, and transmit an indirect memory access response including the data to the requesting core.