Removable Midplanes for Redundant Storage Processor Communication
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Solution Overview
Problem
Information handling systems face challenges in ensuring data integrity, upgradability, and thermal efficiency due to limitations in midplane design and redundancy, which affect the reliability and efficiency of storage processor assemblies.
Innovation Solution
A computing chassis with multiple storage processor assemblies and redundant midplanes that allow independent communication between assemblies, enabling data management and synchronization, with midplanes being removable and upgradable for enhanced availability and thermal efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single midplane is used to couple storage processor assemblies, then device complexity is reduced, but reliability deteriorates due to lack of redundancy
Solution Approach 1:
The patent implements different midplane configurations in different locations within the computing chassis. Multiple midplanes are positioned at different edges of the chassis, each providing localized communication pathways. This local redundancy ensures that if one midplane fails, storage processor assemblies can still communicate through alternative midplanes, thereby improving reliability without requiring a completely redundant system-wide architecture.
Solution Approach 2:
The patent enables dynamic path selection for communication between storage processor assemblies. The system can dynamically route communications through different midplanes based on availability and performance requirements. This dynamic routing capability allows the system to adapt to midplane failures or maintenance scenarios, maintaining reliability while managing complexity through intelligent resource allocation rather than static redundancy.
2Adaptability or versatility
If midplanes are fixed in the computing chassis, then connection stability is improved, but upgradability deteriorates
Solution Approach 1:
The patent divides the midplane system into separate, independently replaceable modules. Each midplane is a discrete component that can be individually removed and replaced without affecting other midplanes or the storage processor assemblies. This segmentation allows specific midplanes to be upgraded, maintained, or replaced while the system remains operational through alternative pathways, thereby improving upgradability while maintaining connection stability through the modular architecture.
Solution Approach 2:
The patent introduces midplanes as intermediary components between storage processor assemblies and the chassis infrastructure. These intermediary midplanes can be independently upgraded or replaced without directly impacting the storage processor assemblies themselves. The midplanes serve as buffer layers that absorb the impact of upgrades, allowing technological advancements in midplane design while maintaining stable connections to the storage processor assemblies through standardized interfaces.
3Reliability
If multiple midplanes are deployed for redundancy, then reliability is improved, but thermal efficiency deteriorates due to reduced air transfer
Solution Approach 1:
The patent positions multiple midplanes at different spatial locations within the computing chassis, specifically at different edges. This spatial distribution across multiple dimensions allows air flow to pass between and around the midplanes, preventing thermal blocking. The three-dimensional arrangement ensures that redundancy is achieved without creating thermal pathways that would trap heat, thereby maintaining thermal efficiency while providing the required system availability through redundant communication pathways.
Data Source
AI summary
A computing chassis, including: a first storage processor assembly; a second storage processor assembly; a first midplane, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the first midplane; and a second midplane, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the second midplane, wherein communication between the first storage processor assembly and the second storage processor assembly is through the first midplane and the second midplane independently.