Removable Sidewall Spacer for High-Aspect-Ratio Gate Structures
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Solution Overview
Problem
The increasing aspect ratio of gate electrode structures in semiconductor devices makes them fragile and prone to damage during processing, leading to issues like inadvertent etching of source and drain regions, which degrades electrical properties and can result in gate oxide undercutting and lifting of the gate structure.
Innovation Solution
A method involving the formation of a removable sidewall spacer and a temporary inverse 'T' structure, using a patterned masking layer and controlled etching to create a stable gate electrode while allowing aggressive etch chemistries, and subsequent ion implantation and annealing steps to form well-defined source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etch processes are used to remove overlying layers, then the etching can remove material, but the source and drain regions are inadvertently damaged and electrical properties are degraded
Solution Approach 1:
A sacrificial spacer layer is introduced as an intermediary protective element between the etch chemistry and the source/drain regions. This spacer acts as a mediator that absorbs the aggressive etching action, preventing direct contact with and damage to the transistor's source and drain regions, thereby maintaining electrical properties while enabling precise material removal elsewhere
Solution Approach 2:
The sacrificial spacer layer is formed in advance before the aggressive etch process. This preliminary protective structure is deposited and patterned to cover vulnerable areas, ensuring that when the aggressive etch chemistry is subsequently applied, the source and drain regions are already protected and cannot be inadvertently damaged
2Productivity
If gate electrode structures are made taller and thinner for increased functionality, then more functionality is achieved in smaller area, but the structures become fragile and prone to damage
Solution Approach 1:
The sacrificial spacer layer serves as a cushioning protective structure formed beforehand that mechanically supports the tall, thin gate electrode structures during subsequent processing. This preliminary protective layer prevents damage to the fragile high-aspect-ratio gate structures by absorbing mechanical stresses and preventing lifting or displacement during aggressive etching and other processing steps
3Productivity
If aggressive etch chemistries are used for small geometries, then etching efficiency is improved, but gate oxide undercutting occurs and gate structure lifting is caused
Solution Approach 1:
The sacrificial spacer layer acts as an intermediary barrier that allows aggressive etch chemistries to be applied efficiently to remove overlying materials while preventing direct interaction between the harsh etch chemistry and the gate oxide. This mediator layer enables high etching efficiency for small geometries without the harmful side effects of oxide undercutting and gate structure lifting
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures accurate control of transistor gate features and source/drain profiles, enabling the use of aggressive etch chemistries for small geometries without damaging the gate structure, maintaining mechanical stability and improving electrical integrity.
Implementation Method 1
A first implant is performed into the substrate using the sidewall spacer and the elevated portion as a mask to form a pair of doped source and drain regions in the substrate
Implementation Method 2
The substrate is annealed
Data Source
AI summary
A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an opening in the patterned masking layer. The first region of the gate electrode layer is partially etched to leave an elevated portion of the gate electrode layer and a lower portion adjacent to the elevated portion. A sidewall spacer is formed adjacent to the elevated portion and over the lower portion. An implant is performed into the semiconductor substrate using the elevated portion and the sidewall spacer as a mask. The sidewall spacer and the lower portion are removed.