Removed Sub-Fin Isolation for Stable Nanoscale Transistors
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in the difficulty of scaling multi-gate and nanowire transistors below the 10 nanometer node, where conventional lithographic processes face constraints in pattern dimension and spacing, leading to issues like residual silicon left after etching and shifts in threshold voltage due to defect introduction.
Innovation Solution
A liquid etchant is used for selective removal of substrate silicon, avoiding damage to epitaxial structures and allowing for uniform etching across features of varying widths and densities, which helps in forming self-aligned sub-fin isolation structures and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic processes are used to scale transistor dimensions below 10nm, then increased device density is achieved, but manufacturing precision deteriorates due to constraints in pattern dimension and spacing
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical structures (nanowires, fins, multi-gate transistors) to achieve higher device density. By stacking multiple active channels vertically, the design overcomes lithographic resolution limits while maintaining manufacturability at current process nodes.
Solution Approach 2:
The patent implements nested structures where multiple nanowires or fins are stacked within a single footprint, creating multi-gate transistors with 3, 4, or more gates. This nesting approach increases effective channel width and device density without requiring proportionally smaller lithographic features.
2Reliability
If substrate silicon is removed to form isolation structures, then device performance is improved, but residual silicon remains causing defect states and threshold voltage shifts
Solution Approach 1:
The patent introduces an intermediary sacrificial layer (such as silicon germanium or oxidized silicon) between the substrate and the final isolation structure. This intermediary layer enables complete and clean removal of substrate silicon through selective etching, preventing residual silicon defects while maintaining epitaxial structure integrity.
Solution Approach 2:
The patent changes the chemical composition and etch selectivity parameters of the removal process by using sacrificial layers with different etch rates than the epitaxial structures. This parameter change enables selective complete removal of substrate silicon without damaging the device structures, eliminating residual silicon defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables damage-free removal of substrate silicon, prevents residual silicon and punch-through issues, and improves transistor performance by reducing defect states and maintaining threshold voltage stability.
Implementation Method 1
A liquid etchant is used for selective removal of substrate silicon, avoiding damage to epitaxial structures and allowing for uniform etching across features of varying widths and densities
Data Source
AI summary
Integrated circuit structures having removed sub-fins, and methods of fabricating integrated circuit structures having removed sub-fins, are described. For example, an integrated circuit structure includes a channel structure, and a sub-fin isolation structure in a trench beneath the channel structure, wherein there is no residual silicon portion in the trench.