Removed-Substrate GAA Nanowire Structure for Leakage Isolation
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in scaling down multi-gate and nanowire transistors, where the constraints on lithographic processes lead to a trade-off between feature size and spacing, and conventional methods for blocking source-to-drain leakage in gate-all-around integrated circuit structures are complex and inefficient.
Innovation Solution
The approach involves removing the silicon substrate using chemical mechanical planarization (CMP) or etching to provide electrical isolation for nanowires or nanoribbons, simplifying the integration of gate-all-around device architectures and eliminating parasitic conduction paths, thereby enabling improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to block source-to-drain leakage in gate-all-around integrated circuit structures, then electrical isolation can be achieved, but the fabrication process becomes complex and inefficient
Solution Approach 1:
The patent removes the substrate entirely to achieve electrical isolation, eliminating the need for complex isolation structures. By extracting the substrate that causes parasitic conduction paths, the invention achieves reliable electrical isolation while simplifying the fabrication process.
Solution Approach 2:
Instead of adding complex structures to block leakage paths in the conventional approach, the invention inverts the approach by removing the substrate itself, thereby achieving isolation through subtraction rather than addition of isolation structures.
2Reliability
If substrate is removed to provide electrical isolation, then parasitic conduction paths are eliminated, but additional processing steps are required
Solution Approach 1:
The substrate removal process is combined with the fabrication of gate-all-around structures in a unified process flow. By merging the substrate removal step with the existing fabrication sequence, the patent eliminates parasitic conduction paths without significantly impacting overall processing efficiency.
Solution Approach 2:
The substrate is removed at an optimal point in the fabrication process where it provides maximum benefit for eliminating parasitic conduction paths. By performing substrate removal preliminarily before subsequent processing steps, the invention achieves thorough parasitic path elimination while streamlining the overall workflow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the integration of nanowire/nanoribbon transistor architectures, reduces substrate leakage, and enhances device performance by allowing for robust source or drain contact from multiple sides, leading to improved device characteristics and lower patterning costs.
Implementation Method 1
The approach involves removing the silicon substrate using chemical mechanical planarization (CMP) or etching to provide electrical isolation for nanowires or nanoribbons
Implementation Method 2
The approach involves removing the silicon substrate using chemical mechanical planarization (CMP) or etching to provide electrical isolation for nanowires or nanoribbons
Data Source
AI summary
Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.