ReRAM Memory Cell Structure Preventing Electrode Bridging
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Solution Overview
Problem
Semiconductor devices, particularly those with resistive random-access memory (ReRAM) in back end of line (BEOL) interconnect stacks, face issues such as exposure of interconnect layers, alignment problems leading to electrode bridging, and thickness inconsistencies, which affect electrical performance and reliability.
Innovation Solution
A semiconductor device structure featuring a memory cell with a bottom electrode, a transitional metal oxide (TMO) layer, TMO sidewall oxides, and spacers on the bottom electrode, which prevents electrode bridging and exposure of lower conducting layers during fabrication, while maintaining compatibility with existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cell structure is formed in BEOL interconnect stack, then memory integration is achieved, but exposure of interconnect layer occurs during memory etching
Solution Approach 1:
The patent applies preliminary action by forming a protective cap structure over the lower conducting layer before the memory cell formation process. This cap structure is prepared in advance to prevent exposure of the interconnect layer during subsequent etching operations, thereby resolving the contradiction between memory integration and interconnect layer protection.
Solution Approach 2:
The patent introduces an intermediary protective cap structure that acts as a mediator between the lower conducting layer and the memory cell etching process. This cap structure serves as a buffer that prevents direct contact between etching agents and the interconnect layer, thus preventing exposure while allowing memory cell formation to proceed.
2Reliability
If contacts are aligned on top electrode of memory, then electrical connection is achieved, but alignment shift leads to electrode bridging or damage to TMO layer
Solution Approach 1:
The patent applies beforehand cushioning by designing the cap structure with extended sidewalls that protrude beyond the memory cell boundaries. These extended sidewalls act as a cushioning barrier that compensates for potential alignment shifts during contact formation, preventing electrode bridging and damage to the TMO layer even when alignment is not perfect.
3Quantity of substance
If feature size is reduced, then device density is improved, but electrical properties deteriorate
Solution Approach 1:
The patent applies local quality by providing enhanced protection specifically at critical areas where feature size reduction causes problems. The cap structure with extended sidewalls provides localized cushioning and protection at the memory cell boundaries, allowing overall device density to increase while maintaining electrical properties through targeted local protection rather than uniform scaling.
Data Source
AI summary
A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.