Render-Cache Controller for Multi-Core Graphics Data Coherency
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Solution Overview
Problem
Multithreading, multi-core graphics processors face challenges in maintaining pixel data coherency and order due to thread-switching, leading to potential incorrect pixel data and increased logic size requirements for separate cache controllers.
Innovation Solution
A streaming render-cache with a render-cache controller that pre-allocates pixel data and uses a single, fully associative content addressable memory to maintain data coherency and order, eliminating the need for two separate CAMs and reducing logic size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate cache controllers are implemented to maintain data coherency and thread dispatch order, then data coherency and processing order are maintained, but the overall logic size increases due to requiring two separate CAMs
Solution Approach 1:
The patent merges the functions of two separate cache controllers into a single unified cache controller that manages both render-cache data coherency and thread dispatch order. This single controller uses one CAM structure to track both cache line status and thread dispatch state, eliminating the need for two separate CAMs and reducing overall logic size while maintaining both data coherency and processing order
Solution Approach 2:
The unified cache controller performs multiple functions: it maintains render-cache data coherency with main memory, tracks thread dispatch order, and manages pixel data allocation. By making the cache controller universal and multi-functional, the patent eliminates redundant control logic and reduces the number of gates required while preserving all necessary control functions
2Reliability
If two separate cache controllers are implemented, then data coherency and thread dispatch order are maintained, but the number of gates required increases
Solution Approach 1:
The patent combines the control logic for maintaining processing order and data coherency into a single cache controller implementation. The unified controller uses shared data structures and control pathways, reducing the total number of gates required compared to implementing two separate controllers with dedicated CAMs for each function
3Productivity
If pixel data is not pre-allocated in the render-cache, then main memory access latency is exposed, but the graphics processor must wait for pixel data fetching from main memory
Solution Approach 1:
The patent implements pre-allocation of pixel data to the render-cache before the graphics processor needs to access it. The unified cache controller anticipates data needs and pre-fetches pixel data from main memory into the render-cache, hiding main memory access latency and allowing the graphics processor to continue processing without waiting for data fetch operations
Data Source
AI summary
A method and apparatus for rendering three-dimensional graphics using a streaming render-cache with a multi-threading, multi-core graphics processor are disclosed. The graphics processor includes a streaming render-cache and render-cache controller to maintain the order in which threads are dispatched to the graphics engine, and to maintain data coherency between the render-cache and the main memory. The render-cache controller blocks threads from being dispatched to the graphics engine out of order by only allowing one sub-span to be in-flight at any given time.