Reorder Buffer Age Determination via Highest Bit XOR

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Solution Overview

Problem

In out-of-order processors, determining the age of instructions in the reorder buffer (ROB) is challenging due to the disruption of age information sequence, making it difficult to identify the oldest instructions for execution and cancellation, especially when branch mis-prediction or exceptions occur.

Innovation Solution

Adding a highest bit to each address in the ROB or branch reorder buffer (B-ROB) and performing an exclusive-OR (XOR) operation with the read pointer (roqhead) to determine the age information of instructions, allowing for accurate identification of the oldest instructions for execution and cancellation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If instructions are executed out-of-order to improve parallelism, then instruction execution speed is improved, but determining the age of instructions becomes difficult

Engineering Contradiction:
Improveinstruction execution speedVSAvoiddifficulty of determining instruction age
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent adds a highest bit dimension to the ROB address to encode temporal information. By modifying the address structure from N bits to N+1 bits and using the highest bit to indicate whether the address is before or after the roqhead, the system能够在二维空间(地址值+最高位)中表达指令的相对年龄关系,从而在乱序执行环境下准确比较指令年龄

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The highest bit acts as an intermediary that mediates the comparison between ROB addresses. Instead of directly comparing full addresses which may be misleading due to wraparound, the XOR operation on highest bits provides a simplified indicator of temporal relationship, making the age comparison process straightforward

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the read pointer (roqhead) flips to maintain sequence tracking, then accurate sequence information is maintained, but direct address comparison becomes invalid

Engineering Contradiction:
Improveaccuracy of sequence informationVSAvoidsimplicity of address comparison
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent performs preliminary encoding of temporal information into the highest bit of the ROB address when the instruction is initially placed in the ROB. This preprocessing step ensures that the age information is already encoded in the address structure, eliminating the need for complex runtime adjustments when roqhead flips occur

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter representation of ROB addresses by adding a highest bit that encodes temporal relationship. This parameter transformation allows the system to maintain accurate sequence tracking while enabling simple XOR-based comparison operations, as the highest bit automatically adjusts with roqhead flips

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If complex comparison logic is used to determine instruction age, then accurate oldest instruction identification is achieved, but hardware area and power consumption increase

Engineering Contradiction:
Improveaccuracy of oldest instruction identificationVSAvoidhardware area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts the essential temporal information from the complex ROB address structure by isolating the highest bit. This extraction approach focuses only on the critical age-indicating bit rather than processing the entire address, significantly reducing the comparison logic complexity while maintaining accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of performing full address comparison or complex temporal analysis, the system applies partial action by only comparing the highest bits of the addresses. This selective comparison using XOR operation achieves accurate age determination with minimal hardware resources, avoiding excessive processing

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11829768B2Method for scheduling out-of-order queue and electronic device items
Publication Date: 2023.11.28 BEIJING VCORE TECH CO LTD
  • US11829768B2 patent drawing
  • US11829768B2 patent drawing
  • US11829768B2 patent drawing

AI summary

The disclosure provides a method for scheduling an out-of-order queue The method includes: adding a highest bit before each address in a reorder buffer (ROB) or in a branch reorder buffer (B-ROB), in which the addresses are entered by instructions in the out-of-order queue; adding a highest bit for a read pointer (roqhead) of the ROB or B-ROB; performing an exclusive-OR (XOR) operation on the highest bit for the roqhead and the highest bit for each of the addresses entered by two instructions to be compared, and determining addresses after the XOR operation as age information of the two instructions; and comparing the age information to determine the oldest instruction in the queue for execution in response to scheduling the out-of-order queue.