Reorder Buffer for Parallel Processing Hazard Repair

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Solution Overview

Problem

As system-on-chip integrated circuits increase in complexity, the interconnect circuitry faces challenges in efficiently communicating access transactions while preventing hazards like transaction ordering violations and coherence breakdowns, which affects performance, latency, and energy consumption.

Innovation Solution

The interconnect circuitry incorporates a reorder buffer for reordering access transactions, processing circuitry for parallel processing operations, and hazard detection and repair circuitry to detect and correct ordering hazards by canceling and repeating specific operations, ensuring independent processing of other transactions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel processing operations are performed on access transactions, then processing speed and productivity are improved, but ordering hazards may arise causing correctness deterioration

Engineering Contradiction:

Improveprocessing speedVSAvoidordering correctness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system segments processing operations into independent parallel tasks that can be executed simultaneously on different access transactions, while using a reorder buffer to maintain correct ordering relationships between transactions. This allows productivity improvement without compromising correctness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The reorder buffer performs preliminary reordering of access transactions before they are processed in parallel, establishing the correct execution order in advance. This preliminary action ensures that when parallel processing completes, the results maintain the required ordering constraints.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If hazard detection and repair operations are implemented, then reliability is improved, but processing latency increases

Engineering Contradiction:

Improvehazard detection accuracyVSAvoidprocessing latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The hazard detection and repair circuitry automatically detects ordering hazards and performs repair operations without external intervention. The system self-corrects by identifying hazards in the reorder buffer and executing repair transactions to restore correct ordering, minimizing manual control and reducing overall latency.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

When an ordering hazard is detected, the system discards the incorrect parallel processing result and recovers by executing a repair transaction that re-applies the correct ordering constraint. This discard-and-recover approach ensures reliability while keeping the complexity of correction minimal.

Inventive Principle:

Principle #34Discarding and recovering

3Adaptability or versatility

If reordering of access transactions is permitted, then adaptability and flexibility are improved, but device complexity increases

Engineering Contradiction:

Improvetransaction reordering capabilityVSAvoidinterconnect circuitry complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The reorder buffer serves multiple functions: it buffers access transactions, reorders them according to dependency constraints, and provides the interface between parallel processing and ordered execution. This multi-functionality improves adaptability while containing complexity within a single structured component.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The reorder buffer acts as an intermediary between the parallel processing circuitry and the execution pipeline, absorbing the complexity of reordering operations. It mediates between the flexibility needed for parallel processing and the strict ordering requirements of the execution environment, simplifying the overall system architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9632955B2Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry

Publication Date: 2017.04.25 ARM LTD

AI summary

A system-on-chip integrated circuit 2 includes interconnect circuitry 4 for communicating transactions between transaction sources and transaction destinations. A reorder buffer 26 serves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.