Microprocessor Reorder Buffer Retirement Ordering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In out-of-order microprocessor architectures, the complexity and resource inefficiency arise from the need to order elements at allocation time, which leads to additional computational and memory constraints, particularly in structures like the re-order buffer and load-store queue, due to diverging ordering behaviors of instructions and memory operations.
Innovation Solution
Elements are ordered at the time of instruction retirement instead of allocation, allowing the write-back module to directly write values into the register file and eliminating the need for upfront ordering, thus freeing resources and reducing the proximity constraint between the re-order buffer and register file, and allowing unordered allocation into structures like the load-store queue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If elements are ordered at allocation time in conventional OOO micro-architectures, then memory operations can acquire and update memory status in program order, but device complexity increases due to tagging and allocation requirements in all resources including the re-order buffer
Solution Approach 1:
The patent inverts the conventional approach by ordering elements at retirement time instead of allocation time. This allows allocation to be simpler while maintaining program order requirements at retirement, effectively reversing when the ordering operation occurs in the instruction lifecycle
Solution Approach 2:
The patent segments the ordering operation from the allocation operation, allowing them to occur at different times. Allocation can place elements in any available slot without ordering constraints, while retirement separately handles the ordering requirement by selecting elements in program order from the allocated slots
2Stability of the object's composition
If elements are ordered at allocation time, then instructions can be dispatched in program order, but loss of time occurs due to the inability to allocate into queues based on element arrival
Solution Approach 1:
The patent inverts the timing of the ordering operation from allocation time to retirement time. This allows allocation to be efficient and based on element arrival, while retirement separately ensures program order is maintained through ordered selection of elements for commitment
3Loss of information
If the re-order buffer performs tagging and allocation at the time of instruction allocation, then elements can be tracked in program order, but device complexity increases due to proximity constraints between the re-order buffer and register file
Solution Approach 1:
The patent inverts when the re-order buffer performs its ordering function, moving it from allocation time to retirement time. This eliminates the need for the re-order buffer to be physically close to the register file, as the buffering and ordering functions are separated in time rather than requiring spatial proximity
Solution Approach 2:
The patent segments the re-order buffer's functions into separate allocation and retirement operations. The buffer allocates slots without ordering constraints, then separately performs ordering at retirement, eliminating the need for complex spatial arrangements and reducing device complexity
Data Source
AI summary
A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.